Samsung Electronics Co., Ltd.

Ji-Eun Lim

Byoung-Jae Bae

Young-Lim Park

Hye-Young Park

Sung-lae Cho

Jin-il Lee

Seung-hwan Lee

Dong-Hyun Im

Yong-Suk Tak

Wan-don Kim

Kyu-Ho Cho

Oh-seong Kwon

Jang-Eun Heo

Beom-Seok Kim

Dong-chul Yoo

Geun-Kyu Choi

Jin-Il Lee

Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.

Semiconductor device having metal plug and method of forming the same

The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.

Metal precursors for low temperature deposition and methods of forming a metal thin layer and manufacturing a phase-change memory device using the metal precursors

A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.

Phase change memory device including resistant material

A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups '&#x2014;N&#x2550;C&#x2550;O', '&#x2014;N&#x2550;C&#x2550;S', &#x201c;&#x2014;N&#x2550;C&#x2550;Se&#x201d;, &#x201c;&#x2014;N&#x2550;C&#x2550;Te&#x201d;, &#x201c;&#x2014;N&#x2550;C&#x2550;Po&#x201d; and &#x201c;&#x2014;C&#x2261;N&#x201d;.

Methods of forming a semiconductor device including a phase change material layer

A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.

High-density probe array

Growing community of inventors

Yongin-si, South Korea

Ji-Eun Lim