Hynix Semiconductor Inc.

Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Skhynix Inc.

Hyundai Electronics Industries Co. Ltd.

Ji-Eun Jang

Seok-Cheol Yoon

Kee-Teok Park

Young-Jun Ku

Ki-Ho Kim

Jae-Jin Lee

Kyung-Whan Kim

Jong-Hee Na

kang-Seol Lee

Bo-Yeun Kim

Min-Sung Choi

Cheal-gi Kim

Seung-ho Baek

Byoung-haw Park

Sang-youn Kim

Shim-Ho Yi

Jeong-Yoon Ahn

Hyoung-wook Kim

Go-Eun Cha

Seung-Hwan Moon

Chang-Hun Lee

Byung-Chul Kim

Chang-Soon Jang

Hoi-Sik Moon

Sun-kyu Joo

Kang-Hyun Kim

Jung-Suk Han

Keun-Chan Oh

Jang-Hyun Kim

Jae-Seob Chung

Duck-Jong Suh

Woo-Young Lee

Gak-Seok Lee

Sung-In Kang

Sun-Kyu Joo

Seong-Nam Lee

Ji-Hye Choi

Jae-Seok Choi

Kyun-Ho Kim

Si-Heun Kim

Won-Gap Yoon

Woo-Jin Jung

Min-Ho Park

Young-Min Choi

Jun-Il Park

Yong-Ju Jeong

Jae-Weon Hur

Seung-Kuk Yun

Jae-Kil Lee

Jin-Hyeong Lee

In-Ok Kim

Jae-Min Seong

In-Seok Song

Ha-Lim Ji

A display device includes: a display panel; and a color conversion panel overlapping with the display panel. The color conversion panel includes: a substrate; a first color conversion pattern on the substrate; a second color conversion pattern on the substrate, and partially overlapping with the first color conversion pattern; a first reflective partition wall between the first color conversion pattern and the second color conversion pattern; a first color filter between the substrate and the first color conversion pattern; and a second color filter between the substrate and the second color conversion pattern.

Color conversion panel with improved light efficiency and display device including the same

A display apparatus includes a gamma controller configured to determine whether the target pixel unit is driven in both time division method and space division method based on a plurality of comparison values and a reference condition, and an output controller configured to generate normal gamma-data of the target pixel unit using a normal gamma curve if the plurality of comparison values satisfy the reference condition and to generate high gamma-data and low gamma-data of the target pixel unit using a high gamma curve and a low gamma curve in both time division method and space division method if the plurality of comparison values do not satisfy the reference condition.

Display apparatus and method of driving the same

A display apparatus includes a display panel which displays an image, a compensation area determiner which divides a display area of the display panel into a compensation area and a normal area, a compensation coefficient determiner which determines a compensation coefficient corresponding to input data of the compensation area, a compensation look up table which stores a noise compensation data which compensates a luminance difference of the compensation area by an interference noise of a light-source driving signal, and a correction data calculator which calculates a correction data corresponding to the input data of the compensation area using the compensation coefficient and the noise compensation data.

A display panel is provided. A first substrate includes a display area and a peripheral area. The peripheral area surrounds the display area. A second substrate is disposed on the first substrate. The second substrate faces the first substrate along a first direction. A liquid crystal layer is interposed between the first substrate and the second substrate. A multi-layered sealant is disposed on the peripheral area of the first substrate. The multi-layered sealant surrounds the liquid crystal layer. The multi-layered sealant includes a first sealant layer including an acrylate resin having a functional group having at least 3 carbon atoms, and a second sealant layer including an epoxy resin having a (meth)arcylate group.

Display panel and method for manufacturing the same

A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

Memory performing target refresh operation and memory system including the same

A method of driving a display panel includes driving a first sub area and a second sub area of a pixel part in a two-dimensional (2D) image mode, wherein a first luminance difference exists between the first and second sub areas in the 2D image mode, and driving the first sub area and the second sub area of the pixel part in a three-dimensional (3D) image mode, wherein a second luminance difference exists between the first and second sub areas in the 3D image mode, the second luminance difference being smaller than the first luminance difference.

Method of driving a display panel and a display apparatus performing the method

A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.

Semiconductor device and testing method thereof

A liquid crystal display device includes; gate lines disposed on a display region, data lines disposed on the display region, wherein the data lines intersect with, and are insulated from, the gate lines, a gate driver which drives the gate lines, a plurality of data drivers which generate a data voltage from an input power source voltage and supply the data voltage to the data lines, and a power source voltage supplying unit which supplies different power source voltages to each of the data drivers according to a distance of each data driver from the gate driver.

Liquid crystal display device and method of driving the same

A liquid crystal composition according to an exemplary embodiment of the present invention includes a liquid crystal compound represented by a below chemical formula (I) at about 10 wt % to about 15 wt %; and at least one liquid crystal compound at about 3 wt % to about 8 wt % among liquid crystal compounds represented by chemical formula (II) to chemical formula (IV). Here, X and Y may be equal to each other or different from each other, and each is an alkyl group or an alkenyl group having a carbon number of 1 to 4.

Liquid crystal composition and liquid crystal display including the same

A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.

Semiconductor memory device and method for testing the same

A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.

Clock control circuit and data alignment circuit including the same

Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.

Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line

A display apparatus and a driving method thereof, in which the display apparatus includes a temperature sensor detecting a temperature, a first memory, a timing controller that receives an (n&#x2212;1)th image signal and an nth image signal of consecutive frames, corrects the nth image signal and outputs the nth image signal, wherein the timing controller generates a clock signal whose phase varies according to the detected temperature, writes the nth image signal in the first memory in synchronization with the clock signal, reads the (n&#x2212;1)th image signal from the first memory, and compares the nth image signal and the (n&#x2212;1)th image signal with each other to then correct the nth image signal based on the comparison result, a data driver that provides an image-data voltage corresponding to the corrected signal of the nth image signal, and a liquid crystal panel that displays an image corresponding to the image-data voltage.

Display apparatus

A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency.

Output enable signal generation circuit for semiconductor memory device

Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line

Growing community of inventors

Kyoungki-do, South Korea

Ji-Eun Jang