Lg Display Co., Ltd.

Ji Eun Chae

Su Hwan Moon

Do Heon Kim

Tae Keun Lee

Sun Young Kwon

Sung Jin Park

Won Seok Kang

Jung Eun Ahn

Byong Wook Shin

A flat panel display device with oxide thin film transistors and a fabricating method thereof are disclosed. The flat panel display device includes: a substrate; gate lines and data lines formed to cross each other and define a plurality of pixel regions on the substrate; the thin film transistors each including an oxide channel layer which is formed at an intersection of the gate and data lines; a pixel electrode and a common electrode formed in the pixel region with having a passivation layer therebetween; and step coverage compensation patterns formed at a step portion formed by the gate line and a gate electrode of the thin film transistor.

Flat panel display device with oxide thin film transistors and method for fabricating the same

A liquid crystal display device including a liquid crystal panel, a gate driver configured to supply gate signals to gate lines on the liquid crystal panel, a data driver configured to supply data voltages to data lines on the liquid crystal panel, and a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines.

Liquid crystal display device and method for driving the same

Disclosed are a TFT array substrate for decreasing a bezel width and a display device including the same. The display device includes a first substrate including a display area (including a pixel formed in a pixel area defined by a gate line and a data line which intersect) and a non-display area that includes a built-in shift register connected to the gate line and a gate link part connected to the built-in shift register, a second substrate facing the first substrate, and a seal pattern formed in the non-display area of the first substrate in correspondence with an edge portion of the second substrate to facing-couple the first and second substrates. The seal pattern includes a first hardening area hardened by a first hardening process, and a second hardening area hardened by a second hardening process.

Display device

A flat panel display device with an oxide thin film transistor and a fabricating method thereof are disclosed. The fabricating method of the flat panel display device includes: preparing a substrate defined into a pixel region and a pad contact region; forming a gate electrode and a link line; forming a pixel electrode within the pixel region; forming an oxide layer on the substrate provided with the pixel electrode; forming a passivation layer on the substrate and performing a formation process of contact holes to expose the link line; and forming a second transparent conductive material film on the substrate.

Flat panel display device with oxide thin film transistor and method for fabricating the same

Disclosed herein is a gate driver which is capable of partially driving a screen. The gate driver includes a first shift register for sequentially outputting n scan pulses (where n is a natural number larger than 2), and a second shift register for selecting p ones (where p is a natural number smaller than or equal to n) of the n scan pulses from the first shift register in response to an external output control signal and supplying the selected p scan pulses respectively to p gate lines of a liquid crystal panel.

Gate driver for partially driving a screen

An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

Apparatus and method for driving liquid crystal display device

A liquid crystal display device includes a plurality of pixel electrodes to which a data voltage is supplied, a plurality of common electrodes arranged to form electric fields with the pixel electrodes, a plurality of common wire lines commonly connected to the common electrodes in each horizontal line, a plurality of common voltage drive circuits to supply a common voltage to each of the corresponding common wire lines, and a controller for generating clock signals to control the common voltage drive circuits to invert an electric potential of the common voltage to be output from each of the common voltage drive circuits for each frame period.

Liquid crystal display

Disclosed in an electrophoretic display device having a charged ink layer. In this disclosed device, the ink layer is disposed on the active region (an image display region) and the peripheral region located around the active region, and an electric field is applied to a portion of the electrophoretic ink film corresponding to the peripheral region. Therefore, the peripheral region does not look stained.

Display device and method of manufacturing the same

A shift register minimizing bias stress applied to transistors is disclosed. A shift register including n stages outputting scan pluses that are sequentially delayed in a forward or reverse direction thereof, where n is positive integer and wherein each stage includes: a scan direction controller that provides a first or second voltage to a scan direction control node according to a first or second enable signal and controlling the forward or reverse direction output; a first node controller that controls a first node according to a voltage on the scan direction control node; a second node controller that controls a second node according to the voltage on the scan direction control node and a voltage on the first node; an output unit that outputs a clock signal as scan pulse according to voltages on the first and second nodes; a third node controller that provides one of the first and second voltages to a third node according to the first and second enable signals; a first discharge circuit unit that discharges the voltage on the first node according to voltages of the second and third nodes; and a second discharge circuit unit that discharges the voltage on the third node according to one of a third enable signal and a fourth enable signal.

Growing community of inventors

Gumi-si, South Korea

Ji Eun Chae