Texas Instruments Corporation

Ji Cheng Yang

Vaiyapuri Venkateshwaran

Kian Teng Eng

Chee Kiang Yew

Goh Jing Sua

A multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; a leadframe for interconnecting semiconductor integrated circuits having a plurality of leads, portions of said leads comprising undulating patterns and a surface metallurgy for promoting solder wetting, said leadframe being disposed between said first and second chips, and said active surface of said first chip positioned in front of said active surface of said second chip; and connections between each of said contact pads of said first chip to one of said leads, respectively, and between each of said contact pads of said second chip to one of said leads, respectively, said connections comprising solder balls, whereby the connections to at least one of said leads are common between said first and second chips.

Multichip semiconductor assembly

A stacked multichip assemblage including a plurality of integrated circuit die directly attached to a substrate having pads corresponding to terminals on the die, and interconnections between the die, and also to external contacts. The stacked integrated circuit arrangement includes a first chip(s) having an array of bumped terminals positioned on the corresponding pads of the substrate, a larger integrated circuit chip having perimeter bump terminals located over the first chip, and the terminals directly bonded to corresponding pads on the substrate.

Stacked flip-chip integrated circuit assemblage

Multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads, and a passive surface; a leadframe for interconnecting semiconductor integrated circuits having first and second surfaces, a plurality of leads, and a chip mount pad, said leadframe being disposed between said first and second chips, and at least a portion of said passive surface of said first chip being attached to said first surface of said chip mount pad; bonding wire connections between each of said contact pads of said first chip to said first surface of one of said leads, respectively; and solder ball connections between each of said contact pads of said second chip to said second surface of one of said leads, respectively, whereby the connections to at least one of said leads are common between said first and second chips.

Multichip assembly semiconductor

A method and apparatus for nondestructive inspection of packaged integrated circuits and defect detection in the integrated circuits. In a scanning acoustic microscopy system, a packaged integrated circuit under test 31 is placed in a tank containing an acoustic transmission medium such as de-ionized water. An acoustic reflector 29 is placed beneath the integrated circuit 31. A pulse-echo mode transducer 17 is used to scan the area containing the integrated circuit 31 with ultrasonic energy. The reflective signal energy is captured by the transducer 17 and the signals are digitized and stored. A computer system analyzes the reflective signal amplitude, and presents a visual image based on where the reflective signal was strong and where it was weak. In a preferred embodiment the image is presented so that the signal from the reflective plate is shown as a dark region where the reflection was weak or zero. It has been determined that those darkened areas will be areas where the integrated circuit under test has delamination or package cracking defects. The visual display can then be used by an operator, or alternatively the data could be analyzed by computer software in an automated system, to determine whether the packaged integrated circuit device under test contains delamination defects.

Method and apparatus for nondestructive inspection and defect detection

An integrated circuit package (30) having first and second layers (76, 78), a plurality of routing pads (82) being integral with the first layer (76), a plurality of upper and lower conduits (18, 118), respectively, disposed on the upper and lower surfaces (92, 94) of the first layer (76), at least one of the upper conduits (18) electrically connected to at least one of the lower conduits (118), a plurality of pads (100) disposed on the second layer (78), vias (84) that electrically connect the pads (100) to the lower conduits (118) and a chip (50) adhered to the second layer (78) having bonding pads (120) at least one of which is electrically connected to at least one of the routing pads (82), is disclosed.

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Singapore, Singapore

Ji Cheng Yang