Oak Technology, Inc.

Plx Technology, Inc.

Jhy-Ping Shaw

William S Wu

Kevin Chiang

Jack Regula

Shengquan Wu

Steven E Olson

Curtis Winward

Ralph Woodard

Ronald A Simmons

A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates requests from other stations and selects a track on which to receive incoming data, and a target that receives the incoming data. The initiator can be connected to a grant multiplexor for selecting a grant line, with the grant multiplexor further including plural smaller multiplexors distributed across the chip. Likewise, the arbiter can be connected to a track multiplexor for selecting a track, with the track multiplexor further including plural smaller multiplexors distributed across the chip. Each station also can include a source queue for queuing outgoing data and a destination queue for queuing incoming data. Preferably, the queues are first-in-first-out registers. The source queue and the destination queue can serve to separate a first clock domain for the on-chip communication bus from a second clock domain for one of the plurality of on-chip components. More than one of the plurality of on-chip components can be coupled to the on-chip communication bus through one of the stations.

On-chip switch fabric

Method and system for determining varying widths of each of a sequence of signal components (marks and spaces) in an incoming digital signal stream and for indicating which mark widths and which space widths fall outside acceptable ranges. A pre-mark and pre-space are added to the front end of the recieved stream for alignment purposes. The width of each signal component (mark or space) is determined and compared with an acceptable range of mark widths or space widths. Each mark or space that lies outside an acceptable range has an indicium associated with this mark or space, indicating this non-compliance. The modified digital signal stream, including the indicia, is re-issued after a selected time delay for subsequent signal processing. A method for measurement or estimation of mark width and space width is presented.

Detection of EFM stream component widths

A method and apparatus for dynamic chaining of DMA operations that includes a count to keep track of control blocks associated with such operations when appended to a current chain of control blocks. The count is checked by a DMA controller upon completing the data-transfer operation associated with each block or each control-block chain depending on the use of a wait bit. Memory used to hold control blocks may be preallocated with anticipated control blocks associated in a predefined linked list to avoid the need for subsequently updating existing control blocks when new blocks are appended to a chain.

High speed dynamic chaining of DMA operations without suspending a DMA controller or incurring race conditions

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San Jose, CA, United States of America

Jhy-Ping Shaw