Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Jhon Jhy Liaw

Ta-Chun Lin

Kuo-Hua Pan

Fang Chen

Min-Chang Liang

Ren-Fen Tsui

Yen-Huei Chen

Dian-Sheg Yu

Hung-Jen Liao

Chih-Hung Hsieh

Chih-Hao Wang

Ching-Wei Tsai

Jonathan Tsung-Yung Chang

Wai-Yi Lien

Cheng Hung Lee

Chiting Cheng

Chih-Yung Lin

Shien-Yang Wu

Pankaj Aggarwal

Chien-Kuo Su

Kuo-Cheng Ching

Kuo-Chiang Ting

Shih-Chi Fu

Chun-Hung Chen

Chun-Jun Lin

Jeng-Jung Shen

Buo-Chin Hsu

Chia-Shiung Tsai

Yu-Jen Wang

Mu-Chi Chiang

Kuan-Lin Yeh

Tzu-Kuei Lin

Yu-Lung Tung

Xiaodong Wang

Chi-Wen Liu

Chih-Hao Chang

Jia-Chuan You

Chun-Sheng Liang

Wei-Hao Wu

Yi-Hsun Chiu

Hua Feng Chen

Min-Yann Hsieh

Bing-Chian Lin

Ying-Jhe Fu

Chien-Chih Chen

Denny Tang

Jyh-Huei Chen

Yuan-Hung Chiu

Ju-Wang Hsu

Yung-Shun Chen

Yi-Chun Huang

Hsiao-Lan Yang

Jiefeng Lin

Yu-Chang Liang

Wesley Lin

Jyun-Yang Shen

Ming-Heng Tsai

Sung-Chun Hsieh

Tung-Heng Shie

Ming-Che Chen

Hung Der Su

Huang-Chao Chang

Chun-Wing Yeung

Wen-Chiang Hong

Dian-Sheng Yu

Chii-Ming W Wu

Kuo Hsien Cheng

Examples of an integrated circuit with a contacting gate structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a memory cell that includes a plurality of fins and a gate extending over a first fin of the plurality of fins and a second fin of the plurality of fins. The gate includes a gate electrode that physically contacts the first fin and a gate dielectric disposed between the gate electrode and the second fin. In some such examples, the first fin includes a source/drain region and a doped region that physically contacts the gate electrode.

Integrated circuits with contacting gate structures

A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Isolation structure for isolating source/drain region structure from adjacent source/drain structure

A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Semiconductor device structure including forksheet transistors and methods of forming the same

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Gate-all-around memory devices

A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins.

FinFET devices with dummy fins having multiple dielectric layers

An exemplary method includes receiving a device layout for a standard cell that includes a transistor and a multilayer interconnect. The multilayer interconnect includes a power line, signal lines, a source contact connected to the power line and a source of the transistor, and a drain contact connected to one of the signal lines and a drain of the transistor. The method includes modifying the device layout for the standard cell. For example, if performance of the standard cell is sensitive to power-related features, the method includes enlarging the power line and the source contact and shrinking the signal lines and the drain contact. If performance of the standard cell is sensitive to signal-related features, the method includes shrinking the power line and the source contact and enlarging the signal lines and the drain contact. A cell height of the standard cell is the same after modifying the device layout.

Interconnect structure design

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Method of manufacturing semiconductor devices and a semiconductor device

A method includes forming a doped region extending in a first direction on a substrate; depositing a gate electrode over the substrate and extending in a second direction; and forming a source/drain region on one side of the doped region; forming a first power rail over an upper surface of the source/drain region, the first power rail extending in the first direction and electrically coupled to the source/drain region; and depositing a second power rail below a lower surface of the source/drain region, the second power rail extending in the first direction and electrically coupled to the source/drain region. The first power rail overlap the second power rail from a top-view perspective.

Semiconductor structure with backside power mesh and method of forming the same

A structure includes first and second cells next to each other and having first and second cell heights, respectively, along a column direction. Each cell includes at least one semiconductor active region extending lengthwise along a row direction perpendicular to the column direction. The structure further includes an array of metal tracks over the first and second cells. The metal tracks are formed by a photolithography process having a half-pitch resolution Rin the row direction. A first pitch of the metal tracks along the row direction is greater than or equal to 2R. At least three rows of the metal tracks are in an area that is directly above the first and second cells and has a height equal to a sum of the first and second cell heights. A row of the metal tracks is disposed across a cell boundary of the first and second cells.

Method and structure for metal tracks in semiconductor devices

A semiconductor device includes first and second active areas, first and second gate structures, and first to third conductive segments. The first and second active areas extend along the first direction. The first and second gate structures cross over the first and second active areas. The first conductive segment crosses over the first and second gate structures, stores a first data signal, and is coupled to the first gate structure, the first and second active areas. The second conductive segment crosses over the first and second gate structures, stores a first complementary data signal, and is coupled to the second gate structure, the first and second active areas. The third conductive segment crosses over the first and second gate structures, and is coupled to the second active area. The first to third conductive segments are arranged in order along a second direction different from the first direction.

Semiconductor device

A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

Hybrid nanostructure and fin structure device

A method includes forming a first transistor comprising a first channel region, a first gate structure surrounding the first channel region, and first source/drain regions on opposite sides of the first gate structure; forming a second transistor comprising a second channel region, a second gate structure surrounding the second channel region, and second source/drain regions on opposite sides of the second gate structure; forming a front-side contact on a top end of a first one of the first source/drain regions of the first transistor; forming a first back-side contact extending from a bottom end of the first one of the first source/drain regions of the first transistor to a bottom end of a first one of the second source/drain regions of the second transistor.

Manufacturing method of semiconductor device having frontside and backside contacts

A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Dielectric fins with different dielectric constants and sizes in different regions of a semiconductor device

An structure includes: first, second, third, fourth, and fifth dielectric fins disposed in this order along a first direction and oriented lengthwise along a second direction; a first semiconductor fin structure disposed between the first and the second dielectric fins; a second semiconductor fin structure disposed between the fourth and the fifth dielectric fins; a third semiconductor fin structure disposed between the second and the third dielectric fins; a fourth semiconductor fin structure disposed between the third and the fourth dielectric fins, where each of the first, the second, the third and the fourth semiconductor fins are oriented lengthwise along the second direction; and gate structures oriented lengthwise along the first direction, where the gate structures engage with one or more of the dielectric fin.

FinFET SRAM cells with dielectric fins

A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.

Fuse cell structure

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Hsinchu County, Taiwan

Jhon Jhy Liaw