Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Jhon Jhy Liaw

Fang Chen

Ta-Chun Lin

Kuo-Hua Pan

Min-Chang Liang

Ren-Fen Tsui

Yen-Huei Chen

Dian-Sheg Yu

Hung-Jen Liao

Chih-Hao Wang

Ching-Wei Tsai

Jonathan Tsung-Yung Chang

Wai-Yi Lien

Chih-Hung Hsieh

Cheng Hung Lee

Chiting Cheng

Chih-Yung Lin

Shien-Yang Wu

Pankaj Aggarwal

Chien-Kuo Su

Kuo-Cheng Ching

Kuo-Chiang Ting

Shih-Chi Fu

Jeng-Jung Shen

Buo-Chin Hsu

Chia-Shiung Tsai

Yu-Jen Wang

Chun-Hung Chen

Chun-Jun Lin

Tzu-Kuei Lin

Chi-Wen Liu

Jia-Chuan You

Wei-Hao Wu

Yi-Hsun Chiu

Mu-Chi Chiang

Kuan-Lin Yeh

Bing-Chian Lin

Ying-Jhe Fu

Chun-Sheng Liang

Chien-Chih Chen

Denny Tang

Jyh-Huei Chen

Yuan-Hung Chiu

Hua Feng Chen

Ju-Wang Hsu

Min-Yann Hsieh

Yung-Shun Chen

Yi-Chun Huang

Hsiao-Lan Yang

Jiefeng Lin

Yu-Chang Liang

Wesley Lin

Yu-Lung Tung

Jyun-Yang Shen

Ming-Heng Tsai

Sung-Chun Hsieh

Tung-Heng Shie

Ming-Che Chen

Chih-Hao Chang

Hung Der Su

Huang-Chao Chang

Dian-Sheng Yu

Chii-Ming W Wu

Kuo Hsien Cheng

Xiaodong Wang

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

FinFET device with source/drain contact extending over dielectric gate

The present disclosure concerns a semiconductor device. An exemplary semiconductor device includes a substrate including top portions isolated by an isolation structure, first semiconductor layers over a first top portion of the substrate in a first region, and a first gate structure wrapping each of the first semiconductor layers and covering a top surface and sidewalls of the first top portion of the substrate extending above the isolation structure. The first semiconductor layers are stacked up and separated from each other, and each first semiconductor layer has a first width. A bottom surface of the first gate structure is below the top surface of the substrate for a first depth which is at least half of the first width.

Nanostructure field-effect transistors including source/drain features with asymmetrical depth

A semiconductor structure includes a substrate, two source/drain (S/D) features; channel layers connecting the S/D features; and a gate structure wrapping around each of the channel layers. The gate structure includes a gate electrode over a gate dielectric layer. The semiconductor structure further includes outer spacers disposed on two opposing sidewalls of the gate structure, inner spacers disposed laterally between the gate structure and each of the two S/D features, a gate-end dielectric feature directly contacting an end of the gate structure, and a gate-top dielectric layer. The gate-end dielectric feature directly contacts the gate electrode. A material in the gate-end dielectric feature has a higher dielectric constant than materials in the outer spacers and the inner spacers. Top surfaces of the gate-top dielectric layer and the gate-end dielectric feature are substantially coplanar. The gate-top dielectric layer is disposed directly above both the gate structure and the outer spacers.

Gate-all-around devices with optimized gate spacers and gate end dielectric

Embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. Bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. In some embodiments, each bit cell includes two word lines.

Memory device and manufacturing thereof

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Implantations for forming source/drain regions of different transistors

A semiconductor structure includes a substrate, a semiconductor fin protruding from the substrate, where the semiconductor fin includes semiconductor layers stacked in a vertical direction, a gate stack engaging with channel regions of the semiconductor fin, and source/drain (S/D) features disposed adjacent to the gate stack in S/D regions of the semiconductor fin. In the present embodiments, the gate stack includes a first portion disposed over the semiconductor layers and a second portion disposed between the semiconductor layers, where the first portion includes a work-function metal (WFM) layer and a metal fill layer disposed over the WFM layer and the second portion includes the WFM layer but is free of the metal fill layer.

Metal gate stacks and methods of fabricating the same in multi-gate field-effect transistors

A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Reducing parasitic capacitance in field-effect transistors

A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Semiconductor device and manufacturing method thereof

Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes receiving a workpiece comprising a first semiconductor element and a second semiconductor element, and a dielectric fin disposed between the first semiconductor element and the second semiconductor element. The method also includes forming a masking layer directly over the dielectric fin, etching the first semiconductor element and the second semiconductor element to form a first recess and a second recess, and forming a first source/drain feature and a second source/drain feature in the first recess and the second recess, respectively. By employing a masking layer and patterning the masking layer to have different widths, a parasitic resistance and a parasitic capacitance of the semiconductor structure may be adjusted accordingly, and undesirably bridging between two adjacent epitaxial source/drain features may be prevented.

Semiconductor strutures with dielectric fins

The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer.

Structure and method for semiconductor devices

Semiconductor devices and semiconductor cell arrays are provided herein. In some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. The multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (FET), and a first p-type FET. The mono-fin active region abuts the multi-fin active region. The mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type FET, and a second p-type FET. The isolation feature is parallel to the first and second gate structures.

Semiconductor device layout

A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Semiconductor structure with high integration density and method for manufacturing the same

An inner sidewall spacer is formed before the formation of the epitaxial source/drain features and an outer sidewall spacer is formed after the epitaxial source/drain features. The two-level sidewall spacer design increases volume of the epitaxial source/drain features, thus improving ion performance. The thicker sidewall spacers also reduce capacitance between source/drain contacts and the gate electrode. In some embodiments, semiconductor nanosheets may be etched to reduce thickness prior to forming replacement gate structures. Nanosheets with reduced thickness improve device swing performance, reduce DIBL effect without sacrificing the channel resistance and epitaxial growth margin.

Semiconductor devices and methods for fabrication thereof

A semiconductor device structure includes a first S/D feature over a first device region of a substrate, a plurality of first semiconductor layers over the first device region of the substrate, and each first semiconductor layer is in contact with the first source/drain feature, a first gate electrode layer surrounding a portion of each first semiconductor layer, and a first dielectric spacer contacting the first S/D feature, the first dielectric spacer disposed between and in contact with two first semiconductor layers of the plurality of the first semiconductor layers. The substrate comprises a first dopant region underneath the first S/D feature and a second dopant region underneath first gate electrode layer and radial outwardly of the first dopant region, the first dopant region comprising first dopants having a first conductivity type and a first dopant concentration and the second dopant region comprising the first dopants having a second dopant concentration less than the first dopant concentration.

Semiconductor device structure and methods of forming the same

A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.

SRAM cells with vertical gate-all-round MOSFETs

Growing community of inventors

Hsinchu County, Taiwan

Jhon Jhy Liaw