Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Jhon Jhy Liaw

Ta-Chun Lin

Fang Chen

Kuo-Hua Pan

Min-Chang Liang

Ren-Fen Tsui

Yen-Huei Chen

Dian-Sheg Yu

Hung-Jen Liao

Chih-Hao Wang

Ching-Wei Tsai

Jonathan Tsung-Yung Chang

Wai-Yi Lien

Chih-Hung Hsieh

Cheng Hung Lee

Chiting Cheng

Chih-Yung Lin

Shien-Yang Wu

Pankaj Aggarwal

Chien-Kuo Su

Kuo-Cheng Ching

Kuo-Chiang Ting

Shih-Chi Fu

Jeng-Jung Shen

Buo-Chin Hsu

Chia-Shiung Tsai

Yu-Jen Wang

Chun-Hung Chen

Chun-Jun Lin

Tzu-Kuei Lin

Chi-Wen Liu

Jia-Chuan You

Wei-Hao Wu

Yi-Hsun Chiu

Hua Feng Chen

Mu-Chi Chiang

Min-Yann Hsieh

Kuan-Lin Yeh

Yu-Lung Tung

Bing-Chian Lin

Ying-Jhe Fu

Xiaodong Wang

Chih-Hao Chang

Chun-Sheng Liang

Chien-Chih Chen

Denny Tang

Jyh-Huei Chen

Yuan-Hung Chiu

Ju-Wang Hsu

Yung-Shun Chen

Yi-Chun Huang

Hsiao-Lan Yang

Jiefeng Lin

Yu-Chang Liang

Wesley Lin

Jyun-Yang Shen

Ming-Heng Tsai

Sung-Chun Hsieh

Tung-Heng Shie

Ming-Che Chen

Hung Der Su

Huang-Chao Chang

Dian-Sheng Yu

Chii-Ming W Wu

Kuo Hsien Cheng

A structure includes first and second cells next to each other and having first and second cell heights, respectively, along a column direction. Each cell includes at least one semiconductor active region extending lengthwise along a row direction perpendicular to the column direction. The structure further includes an array of metal tracks over the first and second cells. The metal tracks are formed by a photolithography process having a half-pitch resolution Rin the row direction. A first pitch of the metal tracks along the row direction is greater than or equal to 2R. At least three rows of the metal tracks are in an area that is directly above the first and second cells and has a height equal to a sum of the first and second cell heights. A row of the metal tracks is disposed across a cell boundary of the first and second cells.

Method and structure for metal tracks in semiconductor devices

A semiconductor device includes first and second active areas, first and second gate structures, and first to third conductive segments. The first and second active areas extend along the first direction. The first and second gate structures cross over the first and second active areas. The first conductive segment crosses over the first and second gate structures, stores a first data signal, and is coupled to the first gate structure, the first and second active areas. The second conductive segment crosses over the first and second gate structures, stores a first complementary data signal, and is coupled to the second gate structure, the first and second active areas. The third conductive segment crosses over the first and second gate structures, and is coupled to the second active area. The first to third conductive segments are arranged in order along a second direction different from the first direction.

Semiconductor device

A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

Hybrid nanostructure and fin structure device

A method includes forming a first transistor comprising a first channel region, a first gate structure surrounding the first channel region, and first source/drain regions on opposite sides of the first gate structure; forming a second transistor comprising a second channel region, a second gate structure surrounding the second channel region, and second source/drain regions on opposite sides of the second gate structure; forming a front-side contact on a top end of a first one of the first source/drain regions of the first transistor; forming a first back-side contact extending from a bottom end of the first one of the first source/drain regions of the first transistor to a bottom end of a first one of the second source/drain regions of the second transistor.

Manufacturing method of semiconductor device having frontside and backside contacts

A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Dielectric fins with different dielectric constants and sizes in different regions of a semiconductor device

An structure includes: first, second, third, fourth, and fifth dielectric fins disposed in this order along a first direction and oriented lengthwise along a second direction; a first semiconductor fin structure disposed between the first and the second dielectric fins; a second semiconductor fin structure disposed between the fourth and the fifth dielectric fins; a third semiconductor fin structure disposed between the second and the third dielectric fins; a fourth semiconductor fin structure disposed between the third and the fourth dielectric fins, where each of the first, the second, the third and the fourth semiconductor fins are oriented lengthwise along the second direction; and gate structures oriented lengthwise along the first direction, where the gate structures engage with one or more of the dielectric fin.

FinFET SRAM cells with dielectric fins

A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.

Fuse cell structure

The present disclosure provides a semiconductor device and a method of forming the same. In an embodiment, the semiconductor device includes a fin extending from a substrate, a gate structure over the channel region, a first spacer extending along a sidewall of the lower portion of the gate structure, and a second spacer extending along a sidewall of the upper portion of the gate structure. The fin includes a channel region and a source/drain (S/D) region adjacent to the channel region. The gate structure includes an upper portion and a lower portion. The second spacer is disposed on a top surface of the first spacer. The first spacer is formed of a first dielectric material and the second spacer is formed of a second dielectric material different from the first dielectric material.

Stacked gate spacers

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

FinFET device with source/drain contact extending over dielectric gate

The present disclosure concerns a semiconductor device. An exemplary semiconductor device includes a substrate including top portions isolated by an isolation structure, first semiconductor layers over a first top portion of the substrate in a first region, and a first gate structure wrapping each of the first semiconductor layers and covering a top surface and sidewalls of the first top portion of the substrate extending above the isolation structure. The first semiconductor layers are stacked up and separated from each other, and each first semiconductor layer has a first width. A bottom surface of the first gate structure is below the top surface of the substrate for a first depth which is at least half of the first width.

Nanostructure field-effect transistors including source/drain features with asymmetrical depth

A semiconductor structure includes a substrate, two source/drain (S/D) features; channel layers connecting the S/D features; and a gate structure wrapping around each of the channel layers. The gate structure includes a gate electrode over a gate dielectric layer. The semiconductor structure further includes outer spacers disposed on two opposing sidewalls of the gate structure, inner spacers disposed laterally between the gate structure and each of the two S/D features, a gate-end dielectric feature directly contacting an end of the gate structure, and a gate-top dielectric layer. The gate-end dielectric feature directly contacts the gate electrode. A material in the gate-end dielectric feature has a higher dielectric constant than materials in the outer spacers and the inner spacers. Top surfaces of the gate-top dielectric layer and the gate-end dielectric feature are substantially coplanar. The gate-top dielectric layer is disposed directly above both the gate structure and the outer spacers.

Gate-all-around devices with optimized gate spacers and gate end dielectric

Embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. Bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. In some embodiments, each bit cell includes two word lines.

Memory device and manufacturing thereof

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Implantations for forming source/drain regions of different transistors

A semiconductor structure includes a substrate, a semiconductor fin protruding from the substrate, where the semiconductor fin includes semiconductor layers stacked in a vertical direction, a gate stack engaging with channel regions of the semiconductor fin, and source/drain (S/D) features disposed adjacent to the gate stack in S/D regions of the semiconductor fin. In the present embodiments, the gate stack includes a first portion disposed over the semiconductor layers and a second portion disposed between the semiconductor layers, where the first portion includes a work-function metal (WFM) layer and a metal fill layer disposed over the WFM layer and the second portion includes the WFM layer but is free of the metal fill layer.

Metal gate stacks and methods of fabricating the same in multi-gate field-effect transistors

A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Reducing parasitic capacitance in field-effect transistors

Growing community of inventors

Hsinchu County, Taiwan

Jhon Jhy Liaw