United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Jhih-Yuan Chen

Kun-Ju Li

Chau-Chung Hou

Hsin-Jung Liu

Ang Chan

Wei-Xin Gao

Chun-Han Chen

I-Ming Lai

Zong-Sian Wu

Fu-Shou Tsai

Wen-Chin Lin

Yu-Lung Shih

Ji-Min Lin

Fu-Chun Hsiao

Syue-Ren Wu

Meng-Hsun Wu

Hsiang-Chi Chien

A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

Semiconductor assembly and method for manufacturing the same

A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Method for manufacturing semiconductor device

An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

Alignment mark structure and method of fabricating the same

A semiconductor device includes a substrate having a memory region and a peripheral region defined thereon, wherein the peripheral region comprises at least one transistor, the memory region comprises a plurality of memory cells, each memory cell comprises at least one gate structure and a capacitor structure, a mask layer disposed on the capacitor structure in the memory region, and a dielectric layer disposed on the substrate within the peripheral region, wherein a top surface of the dielectric layer is aligned with a top surface of the mask layer.

Semiconductor device and manufacturing method thereof

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Kaohsiung, Taiwan

Jhih-Yuan Chen