Taiwan Semiconductor Manufacturing Comp. Ltd.

Jhih-Bin Chen

Ming Chyi Liu

Chien-Chih Chou

Alexander Kalnitsky

Kong-Beng Thei

Yi-Huan Chen

Chen Yu Chen

Shih-Chung Hsiao

Chia-Shiung Tsai

Eugene Chen

Yu-Chang Jong

Hung-Shu Huang

Jhu-Min Song

Yu-Lun Lu

Tsung-chieh Tsai

Yi-Kai Ciou

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Boundary design for high-voltage integration on HKMG technology

Some embodiments relate to a method for forming a vertical cavity surface emitting laser (VCSEL) structure. The method includes forming an optically active layer over a lower reflective layer and forming an upper reflector over the optically active layer. A first spacer is formed along sidewalls of the upper reflector. An oxidation process is performed with the first spacer in place to oxidize a peripheral region of the optically active layer. A first etch process is performed on the lower reflective layer and the oxidized peripheral region, thereby forming a lower reflector and an optically active region.

Techniques for vertical cavity surface emitting laser oxidation

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. A plurality of separate isolation structures are disposed within the substrate. The plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. A gate electrode is disposed within the substrate. The gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.

High voltage device with gate extensions

A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Semiconductor structure and forming method thereof

The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess;

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Various embodiments of the present disclosure are directed towards a method for forming a vertical cavity surface emitting laser (VCSEL) device. The method includes forming a bond bump and a bond ring over a substrate. A semiconductor die is bonded to the bond ring. A molding layer is formed around the semiconductor die. The molding layer is laterally offset from a cavity between the semiconductor die and the substrate. A VCSEL structure is formed over the bond bump.

Bump bonding structure to mitigate space contamination for III-V dies and CMOS dies

A vertical cavity surface emitting laser (VCSEL) device includes a microlens arranged over a reflector stack. The reflector stack includes alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer includes a first average concentration of a first element and has a first width. The second lens layer includes a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer includes a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.

VCSEL with self-aligned microlens to improve beam divergence

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

Some embodiments relate to a vertical cavity surface emitting laser (VCSEL) device including a VCSEL structure overlying a substrate. The VCSEL structure includes a first reflector, a second reflector, and an optically active region disposed between the first and second reflectors. A first spacer laterally encloses the second reflector. The first spacer comprises a first plurality of protrusions disposed along a sidewall of the second reflector.

A memory device and method of making the same are disclosed. The memory device includes a first split gate memory cell including a first memory stack located over a substrate. The first memory stack includes a first floating gate and a first control gate located above the first floating gate. The split gate memory cell also includes a first select gate located adjacent to the first floating gate and the first control gate and a contact etch stop located over a portion of a top surface of the first select gate. The contact etch stop enables a narrowing of the drain contact via during an etch process. By narrowing the drain contact via, the density of split gate memory cells may be increased.

Third generation flash memory structure with self-aligned contact and methods for forming the same

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

Structures for bonding a group III-V device to a substrate by stacked conductive bumps

Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.

Some embodiments relate to a method for manufacturing a vertical cavity surface emitting laser. The method includes forming an optically active layer over a first reflective layer and forming a second reflective layer over the optically active layer. Forming a masking layer over the second reflective layer, where the masking layer leaves a sacrificial portion of the second reflective layer exposed. A first etch is performed to remove the sacrificial portion of the second reflective layer, defining a second reflector. Forming a first spacer covering outer sidewalls of the second reflector and masking layer. Performing an oxidation process to oxidize a peripheral region of the optically active layer. A second etch is performed to remove a portion of the oxidized peripheral region, defining an optically active region. Forming a second spacer covering outer sidewalls of the first spacer, the optically active region, and the first reflector.

Growing community of inventors

Hsinchu, Taiwan

Jhih-Bin Chen