Taiwan Semiconductor Manufacturing Comp. Ltd.

Jheng-Si Su

Shih-Ho Lin

Jen-Chieh Lai

Yu-Chen Wei

Chun-Chieh Chan

Chih-Yuan Yang

Feng-Inn Wu

Huang-Jen Hsu

Po-Ting Huang

Tzuyi Hsieh

Kung-Ming Liu

Zhi-Sheng Hsu

The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.

CMP safe alignment mark

A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.

Chemical mechanical polishing apparatus and method

A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.

Chemical mechanical polishing method

A chemical mechanical polishing apparatus is provided. The chemical mechanical polishing apparatus includes a polishing pad, a pad conditioner, a measurement tool, and a controller. The polishing pad is provided in a processing chamber for polishing a wafer placed on the polishing surface of the polishing pad. The pad conditioner is configured to condition the polishing surface. The measurement tool is provided in the processing chamber and configured to measure the downward force of the pad conditioner. The controller is coupled to the pad conditioner and the measurement tool, and is configured to adjust the downward force of the pad conditioner in response to an input from the measurement tool.

A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.

Article transporter in semiconductor fabrication

A method for forming a semiconductor device structure is provided. The method includes providing a wafer over a polishing platen. The wafer includes a metal layer and a dielectric layer. The metal layer covers the dielectric layer and fills an opening of the dielectric layer. The method also includes polishing the wafer using a first operation to thin down the metal layer. The first operation has a first polishing selectivity of the metal layer to the dielectric layer. The method further includes polishing the wafer using a second operation to further thin down the metal layer until the dielectric layer is exposed. The second operation has a second polishing selectivity of the metal layer to the dielectric layer. The second polishing selectivity is different from the first polishing selectivity. The first operation and the second operation are performed in-situ on the polishing platen.

Polishing process for forming semiconductor device structure

A method for transporting an article used in semiconductor fabrication is provided. The method includes moving a first transporter next to an article to have the article faces a plurality of gas holes formed on the first transporter; suspending the article with the first transporter in a non-contact manner by providing a flow of gas through the gas holes of the first transporter; and transferring the article with the first transporter while the flow of gas is continuously provided.

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Zhubei, Taiwan

Jheng-Si Su