Nan Ya Technology Corporation

Jhen-Yu Tsai

Tseng-Fu Lu

Wei-Ming Liao

Yu-Ping Chen

Shih-Ting Lin

Chiang-Lin Shih

Chin-Ling Huang

Yi-Ju Chen

Ching-Chia Huang

Jei-Cheng Huang

Cheng-Hsien Hsieh

Cheng-Han Yang

A memory includes a data storage device, a data processing device, and a contact element. The data processing device is disposed over the data storage device. The contact element is disposed between the data storage device and the data processing device. The contact element electrically connects the data storage device with the data processing device.

Memory with a contact between a data storage device and a data processing device

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode. The lower gate electrode and the upper gate electrode are spaced apart from the substrate by different distances, and the lower gate electrode and the upper gate electrode are configured to receive different voltages.

Buried gate semiconductor device with reduced gate induced drain leakage

A semiconductor device is provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The gate structure includes a lower gate electrode and an upper gate electrode over the lower gate electrode. The gate structure also includes a first barrier layer disposed between the lower gate electrode and the upper gate electrode. The gate structure also includes a first dielectric layer disposed between the lower gate electrode and the upper gate electrode. The first dielectric layer is adjacent to the first barrier layer.

Semiconductor device having buried gate structure

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a first doped structure over a substrate and a second doped structure over the first doped structure and the substrate; a first gate layer, at last partially disposed between the first doped structure and the second doped structure; a first gate dielectric layer, surrounding the first gate layer; a channel layer, surrounding the first gate dielectric layer; a second gate dielectric layer, surrounding the channel layer; and a second gate layer, surrounding the second gate dielectric layer. A manufacturing method for forming the same is also provided.

Semiconductor structure including multiple gate electrodes

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a trench in a substrate and disposing a lower gate electrode in the trench. The method also includes disposing a first dielectric layer on the lower gate electrode in the trench and partially removing the first dielectric layer to expose a portion of the lower gate electrode.

Method for manufacturing semiconductor device having buried gate structure

A method of manufacturing a semiconductor memory is provided. The method includes steps of forming a data storage device; forming a data processing device over the data storage device; forming a contact element electrically connected to the data storage device; and forming a data processing device over the data storage device and electrically connected to the contact element.

Method for manufacturing a semiconductor memory

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode.

Buried gate semiconductor device having a dielectric layer between two electrodes

The present application provides a method for manufacturing a memory device having a word line (WL) with dual conductive materials. The method includes steps of providing a semiconductor substrate with an active area defined adjacent to a surface of the semiconductor substrate; forming a recess extending from the surface into the semiconductor substrate; disposing a first insulating layer conformal to the recess; disposing a first conductive material within the recess and surrounded by the first insulating layer; removing a portion of the first conductive material to form a first conductive member; disposing a second insulating layer within the recess and conformal to the first insulating layer and the first conductive member; and disposing a second conductive material within the recess and surrounded by the second insulating layer to form a second conductive member adjacent to the first conductive member.

Method for manufacturing memory device having word line with dual conductive materials

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.

Method for manufacturing semiconductor device with passing gate

A memory structure is described, which includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a capping layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The capping layer covers the word line. The capping layer includes a first material film, and a dielectric constant of the first material layer is smaller than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the capping layer. The bit line is disposed over the bit line contact and electrically connected to the bit line contact.

Memory structure including low dielectric constant capping layer

A semiconductor device is provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes an upper gate electrode, a capping layer on the upper gate electrode and a first dielectric layer partially disposed between the upper gate electrode and the capping layer.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first vertical transistor and a second vertical transistor adjacent to the first vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The semiconductor device further includes a dielectric layer wrapping upper portions of the first word line and the second word line, and an air gap inserted between lower portions of the first vertical transistor and the second vertical transistor.

Semiconductor device

A semiconductor device with a passing gate is provided. The semiconductor device includes a substrate having a first trench and a first gate structure in the first trench. The first gate structure includes a first gate electrode having a first doped region.

Semiconductor device with passing gate

A method for manufacturing a semiconductor device is provided. The method includes forming a trench in a substrate; disposing an upper gate electrode in the trench; disposing a first dielectric layer on the upper gate electrode in the trench; and disposing a capping layer on the first dielectric layer in the trench.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes providing a precursor structure including a first capacitor and a second capacitor on a substrate; forming a first vertical transistor and a second vertical transistor respectively over the first capacitor and the second capacitor, in which the first vertical transistor includes a first word line having a first top width and a first bottom width smaller than the first top width, the second vertical transistor includes a second word line having a second top width and a second bottom width smaller than the second top width; and forming an air gap between the first vertical transistor and the second vertical transistor.

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Kaohsiung, Taiwan

Jhen-Yu Tsai