Macronix International Co., Ltd.

Jhen-Sheng Chih

Shang-Chi Yang

Su-Chueh Lo

Jian-Syu Lin

A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.

Duty cycle correction method and duty cycle correction system

A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.

High-speed, low distortion receiver circuit

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

Robust power-on-reset circuit with body effect technique

A circuit to generate complementary signals comprises a first string of inverters with two inverters in series to produce a true signal in response to an input signal, and a second string of inverters with three inverters in series to produce a complement signal in response to the input signal. A compensation capacitance circuit is connected to a node in the first string of inverters. The compensation capacitance circuit can add capacitance to the node to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions an inverter in the second string of inverters.

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Hsinchu, Taiwan

Jhen-Sheng Chih