Samsung Electronics Co., Ltd.

Jeunghwan Park

Inho Kang

Jinwoo Park

Yongsung Cho

Taehyo Kim

Sunghoon Kim

Chanho Kim

Bongsoon Lim

Pansuk Kwak

Hongsoo Jeon

Chaehoon Kim

YongSung Cho

Ansoo Park

Dongha Shin

Jeawon Jeong

A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.

Page buffer circuit and memory device including the same

Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.

Semiconductor memory device including a capacitor

The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.

Nonvolatile memory devices and storage devices including nonvolatile memory devices

Growing community of inventors

Suwon-si, South Korea

Jeunghwan Park