Stmicroelectronics S.r.l.

Jesus Guinea

Luciano Tomasini

Carlo Maria Milanese

Rinaldo Castello

Massimiliano Rutar

Santo Maggio

A method and an equalizer circuit equalize signals transmitted on a line having an attenuation. The equalizer circuit includes: an analogical adaptive filter applied in series with the line and includes plural transconductance filters each having a bias current. The adaptive filter has a pole and a zero each having a frequency position in the working band that is variable in response to the bias current. The equalizer circuit includes a retroaction circuit applied to the output of the filter and able to vary the bias current according to the varying of the attenuation of the line. The bias current of the transconductance filters has a prefixed value and is made to vary at the increasing of the attenuation so that the pole is moved toward high frequencies and the zero is moved toward low frequencies.

Equalizer

A bidirectional synchronous interface for the reception of a first flow of digital data with a first coding from a communication channel, and for the transmission on the communication channel of a second flow of digital data with the first coding in synchrony with a local timing signal. The interface includes a synchronization circuit for synchronizing the interface with the first flow of digital data that includes a first circuit fed by the local timing signal to generate, starting from the local timing signal, a plurality of repetition timing signals delayed from one another by fractions of a period, and a second circuit means fed by the first flow of digital data and by the plurality of repetition timing signals suitable for determining, from the plurality of repetition timing signals, a pre-selected repetition timing signal substantially in synchrony with the first flow of digital data.

Bidirectional synchronous interface with single time base

A detector detects timing in a digital data flow with a bit-time equal to T. A first circuit generates four local timing signals each having periods substantially equal to the bit-time. Each of the four local timing signals are out of phase with one another by &#xbc; period. A second circuit samples the four local timing signals upon each transition of a first type for determining, based upon the sampling, whether two of the four local timing signals forming a pair of reference signals that are out of phase by &#xbd; period are advanced or delayed relative to the timing of the data flow. The second circuit controls the first circuit for delaying or advancing the four local timing signals based upon the pair of reference signals.

Detector for detecting timing in a data flow

A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Synchronism phase-switching circuit for the recovery of received data

The present invention relates a circuit for generating a digital output signal ( ) locked to a phase of an input signal ( ), comprising a plurality of delay cells ( ), a first register ( ) containing a first value, a phase detector ( ) and a control logic ( ), which is characterized by comprising a plurality of flip-flop devices ( ), wherein storing said first value, a second register ( ) containing a second value, a plurality of adder nodes ( ) adapted to sum in each of said delay cells ( ) said second value with the content of said selected flip-flop device ( ), being said delay cells ( ) adapted to provide said digital output signal ( ), said phase detector ( ), receiving said input signal ( ) and said digital output signal ( ), adapted to detect the phase difference ( ) between said input signal and said digital output signal ( ), said control logic ( ) adapted to control said first and second value in function of said phase difference ( ). (FIG.

Delay locked loop circuit with convergence correction

An amplifier stage for a buffer with negative feedback includes an input stage having an input terminal, an output terminal, a first and a second supply terminal, a biasing branch, a first and a second balancing branch each comprising an active transistor for supplying, at the output terminal, a current depending on the current difference in the first and second balancing branches. The biasing branch and the first and second balancing branches are connected in parallel between the first and second supply terminals. The input terminal divides the biasing branch into two input branches having a constant-current generator. Each active transistor is connected to a corresponding current generator for receiving a control voltage correlated with a voltage at the terminals of the current generator.

Input stage for a buffer with negative feed-back

A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals includes a plurality of bistable means, an EXOR type logical gate, a presynchronization device and a combinatory logic device capable of creating a CMI type binary signal by codifying with an identical circuit path the &ldquo;1&rdquo; bits and &ldquo;0&rdquo; bits, sequence of bit present in the NRZ type binary signals.

Circuit system suitable for codifying NRZ type binary signals into CMI type binary signals

The difference between the Vgs voltages of first and second MOS transistors of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a compensation circuit. The compensation circuit includes third and fourth MOS transistors that are the same type as the first and second transistors. These transistors are all formed in the same integrated circuit. The compensation circuit includes a bias circuit for biasing the third and fourth transistors, and a measurement circuit for measuring the difference between the Vgs voltages of the third and fourth transistors. The compensation circuit further includes a current compensation circuit for generating a compensation current that is a function of the difference measured, and a modification circuit for modifying the biasing of the first and second MOS transistor using the compensation current.

Circuit for compensating for the difference between the Vgs voltages of two MOS transistors

A delay-locked loop circuit (DLL) includes a delay line with a delay which can be varied in a controlled manner to delay a periodic input signal having a period T, and a control circuit for controlling the delay line to lock the delay to the period T. The delay line supplies to the control circuit a plurality of periodic signals each delayed relative to the periodic input signal by a respective fraction of the delay. The control circuit includes a sequence-detector circuit which can periodically detect in the delayed signals characteristic sequences of digital values indicative of the delay. The control circuit can bring about a reduction or an increase in the delay for locking to the period T based upon the detected types of characteristic sequences.

Delay-locked loop circuit

The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

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Brembate, Italy

Jesus Guinea