Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique

Stmicroelectronics S.a.

Stmicroelectronics (rousset) Sas

Jessy Bustos

Philippe Coronel

Romain Wacquez

Philippe Thony

Thomas Skotnicki

Christophe Regnier

Laurent Pain

François Wacquant

Serdar Manakli

Brice Tavel

A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.

Method for manufacturing a transistor with parallel semiconductor nanofingers

A method is for producing an asymmetric architecture semiconductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.

Method of producing an asymmetric architecture semi-conductor device

Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.

Transistor and fabrication process

A first circuit element, which is reflective, is formed. A first layer, which is attenuating, is formed. above the first circuit element. A second layer, which is transparent, is formed above the first layer to fill an aperture in the first layer. An overlying lithography resist layer is then exposed to a radiation flux level below a development threshold but high enough that a sum of the radiation flux level and a reflected secondary radiation flux level exceeds the development threshold. The lithography resist layer is developed so as to obtain a mask having an opening through which the first and second layers are removed to form a second aperture which is filled to form a second circuit element.

Production of two superposed elements within an integrated electronic circuit

An integrated electronic circuit includes a cavity buried in a substrate. A surface of the substrate has a depression aligned above the buried cavity. The depression is filled with a material selected so that reflection of a lithography radiation on the substrate surface is attenuated. A resist layer is deposited on the circuit and then exposed to the radiation so that those resist portions which are located above the depression and those located away from the depression receive amounts of radiation that are below and above, respectively, the development threshold of the resist. An etching mask is therefore obtained on the circuit, which is aligned with respect to the cavity and its associated surface depression.

Method for the formation of an integrated electronic circuit having a closed cavity

A process for producing an electronic component includes covering a substrate with a portion defining, with the substrate, a volume at least partly filled with a temporary material. The temporary material is then removed via chimney for access to said volume. A deposition of a fill material is then made in said volume, the fill material being obtained from precursors supplied via the chimney. The process is particularly suitable for producing a gate of an MOS-type transistor. In this case, the fill material is conducting or semiconducting, and an electrically insulating coating material may also be deposited in said volume before the (semi) conducting fill material. The process also includes defining a trench in a substrate filled with a temporary material. The filled trench is then covered with a circuit portion. The temporary material is then removed via a chimney for access to the trench. A deposition of low dielectric fill material is then made in the trench.

Growing community of inventors

Le Touvet, France

Jessy Bustos