Micron Technology Incorporated

Jessica Chen

Karthik Sarpatwari

Nevil N Gajera

Fabio Pellizzer

Lingming Yang

Yen Chun Lee

Mingdong Cui

Joseph M McCrate

Francesco Douglas Verna-Ketel

Josephine Tiu Hamada

Xuan-Anh Tran

Jason A Durand

Amitava Majumdar

Xuan Anh Tran

Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

Dirty write on power off

Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

Accessing a multi-level memory cell

Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.

Self-selecting memory cells configured to store more than one bit per memory cell

Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.

Programming intermediate state to store data in self-selecting memory cells

Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

Dynamic read voltage techniques

Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device

Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

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Boise, ID, United States of America

Jessica Chen