Intel Corporation

Jesse Z Fang

Bratin Saha

Rajiv Gupta

Hu Tiger Chen

Shoumeng Yan

Ying Gao

Mohan Rajagopalan

Avi Mendelson

Peinan Zhang

David A Berson

Youfeng Wu

Xiaocheng Zhou

Dawei Wang

Shaojun Wei

Leibo Liu

Sun C Chan

Shouyi Yin

Jiqiang Song

Zhou Xiaocheng

Randolph Wang

Eugene Tang

Ali Reza Adl-Tabatabai

Paul Peng

Hu Chen

A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.

Extending the capabilities of existing devices without making modifications to the existing devices

Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Shared virtual memory

A hierarchical software profiling mechanism that gathers hierarchical path profile information has been described. Software to be profiled is instrumented with instructions that save an outer path sum when an inner region is entered, and restore the outer path sum when the inner region is exited. When the inner region is being executed, an inner path sum is generated and a profile indicator representing the inner path traversed is updated prior to the outer path sum being restored. The software to be profiled is instrumented using information from augmented control flow graphs that represent the software.

Hierarchical software path profiling

A speculative code reuse mechanism includes a reuse buffer, a main processing core and a reuse checking core. The reuse buffer includes inputs and outputs of previously executed instances of code reuse regions. Aliased reuse regions are regions that access memory locations that may change between executions of the region. When an aliased code reuse region is encountered and a matching instance exists in the reuse buffer, the main core speculatively executes code occurring after the reuse region, while the reuse checking core executes code from the reuse region to verify the matching instance. If the matching instance is verified, the speculative execution is committed, and if the matching instance is not verified, the speculative execution is squashed.

Speculative reuse of code regions

A method and apparatus for optimizing code using resource based partial elimination techniques is disclosed. At least one location is identified in the code wherein the at least one location has available resources. One of the plurality of instructions is moved to the at least one location according to partial elimination techniques.

Optimizing code based on resource sensitive hoisting and sinking

A method and apparatus for optimizing execution of code is disclosed. The code is executed to generate path profiling information. At least one location is identified for relocating at least one of the plurality of instructions in the code, where the at least one location is enabled by one of predication and speculation. A cost and a benefit are calculated for relocating the at least one of the plurality of instructions to the at least one location, the cost and the benefit based on the path profiling information. The at least one of the plurality of instructions is moved to the at least one location when the benefit exceeds the cost, and one of predication and speculation is performed on the one of the plurality of instructions. The code is then reexecuted.

Optimizing code by exploiting speculation and predication with a

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San Jose, CA, United States of America

Jesse Z Fang