Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Jesse Thilo

Paul Gerard D'Arcy

Kent E Wires

Sanjay Jinturkar

C John Glossner

Dean Batten

Richard Joseph Byrne

Eu Gene Goh

Silvester Tjandra

Stamatis Vassiliadis

Nevin C Heintze

Nigamanth Lakshminarayana

Kerry D Snyder

Vitaly A Zelov

In one embodiment, a method for accessing a physical storage-device array comprising a plurality of storage devices. The method includes (1) obtaining at least one parameter from a profile selected from two or more profiles concurrently defining two or more virtual arrays, each profile defining (i) a different virtual array associated with a corresponding set of storage devices and (ii) a parameter set of one or more parameters used for accessing the virtual array; and (2) generating an instruction, based on the at least one parameter, for accessing information to the virtual array defined by the selected profile.

Virtual profiles for storage-device array encoding/decoding

In one embodiment, a method for reading data from a storage-device array including three or more storage devices. The array has a plurality of sector levels, each sector level containing one sector on each storage device in the array at corresponding addresses across the storage devices. Each sector level includes (i) parity data stored on a first storage device and (ii) information stored on the two or more remaining storage devices. The parity data for a current sector level is generated from the information stored at the current sector level on the remaining storage devices. The method includes: (a) generating an instruction for reading (i) the parity data from the first storage device at the current sector level and (ii) the information from the remaining storage devices at the current sector level; (b) receiving an indicator indicating whether one of the remaining storage devices is a degraded storage device; (c) if the indicator does not indicate a degraded storage device, then providing as output the information read from the remaining storage devices at the current sector level; and (d) if the indicator does indicate a degraded storage device, then: (d1) reconstructing information previously stored on the degraded storage device at the current sector level based on (i) the parity data read from the first storage device at the current sector level, and (ii) the information read from each remaining non-degraded storage device at the current sector level; and (d2) providing as output (i) the information read from the one or more non-degraded storage devices at the current sector level and (ii) the reconstructed information.

Back-annotation in storage-device array

The present invention provides a reduction checksum generator for calculating a checksum value for a block of data. In one embodiment, the reduction checksum generator includes a reduction unit having a plurality of reduction stages and configured to pipeline a plurality of segments of the block of data through the plurality of reductions stages to reduce the plurality of segments to at least two segments. The reduction checksum generator also includes a checksum unit configured to generate a one's complement sum of the at least two segments and invert the one's complement sum to produce the checksum value. In addition, a method of calculating checksum value using reduction for a block of data and a parallel reduction checksum generator are also disclosed.

Reduction checksum generator and a method of calculation thereof

A checksum calculator employs a tree structure of reduction stages to process words of a checksum data array. The number of words in the checksum data array is compared to the number of words each of the reduction stages might process. If the number of words in the checksum data array is greater than the number of words that the highest level reduction stage might process, then a portion of the checksum data array is processed, remaining words of the checksum data array are appended to the processed portion, and the process is repeated. If the number of words in the checksum data array is less than or equal to the number of words that the highest level reduction stage might process, then the checksum data array is processed by the lowest level reduction stage that can process the entire checksum data array.

Checksum calculator with tree structure of reduction stages

The invention provides techniques for reducing the power consumption of pipelined processors. In an illustrative embodiment, the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e.g, by execute and writeback stages. The predicate dependencies can be handled using, e.g., a virtual single-cycle execution technique which locks a predicate register while the register is in use by a given instruction, and then stalls subsequent instructions that depend on a value stored in the register until the register is unlocked. As another example, the predicate dependencies can be handled using a compiler-controlled dynamic dispatch (CCDD) technique, which identifies dependencies associated with a set of instructions during compilation of the instructions in a compiler. One or more instructions are then grouped in a code block which includes a field indicating the dependencies associated with those instructions, and the instructions are then, e.g., either stalled or decoded serially, based on the dependencies present in the code block. By eliminating unnecessary processing for false-predicate instructions, the invention significantly reduces the power consumption of the processor.

Method and apparatus for reducing power consumption in a pipelined processor

A pipelined processor is configured to provide virtual single-cycle instruction execution using a register locking mechanism in conjunction with instruction stalling based on lock status. In an illustrative embodiment, a set of register locks is maintained in the form of a stored bit vector in which each bit indicates the current lock status of a corresponding register. A decode unit receives an instruction fetched from memory, and decodes the instruction to determine its source and destination registers. The instruction is stalled for at least one processor cycle if either its source register or destination register is already locked by another instruction. The stall continues until the source and destination registers of the instruction are both unlocked, i.e., no longer in use by other instructions. Before the instruction is dispatched for execution, the destination register of the instruction is again locked, and remains locked until after the instruction completes execution and writes its result to the destination register. The decode unit can thus dispatch instructions to execution units of the processor as if the execution of each of the instructions completed in a single processor cycle, in effect ignoring the individual latencies of the execution units. Moreover, the instructions can be dispatched for execution in a program-specified order, but permitted to complete execution in a different order.

Virtual single-cycle execution in pipelined processors

The invention provides techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions. In an illustrative embodiment, a compiler is used to identify pipeline dependencies in a given set of instructions. The compiler then groups the set of instructions into a code block having a field which indicates the types of pipeline dependencies, if any, in the set of instructions. The field may indicate the types of pipeline dependencies by specifying which of a predetermined set of hazards arise in the plurality of instructions when executed on a given pipelined processor. For example, the field may indicate whether the code block includes any Read After Write (RAW) hazards, Write After Write (WAW) hazards or Write After Read (WAR) hazards. The code block may include one or more dynamic scheduling instructions, with each of the dynamic scheduling instructions including a set of instructions for execution in a multi-issue processor.

Compiler-controlled dynamic instruction dispatch in pipelined processors

A processor is configured to include at least two architecturally-distinct storage spaces, such as, for example, a stack for storing control operands associated with one or more instructions, and a register file for storing computational operands associated with one or more instructions. The processor further includes a datapath which is at least partially shared by the stack and register file, a multiplexer operative to select an output of either the stack or the register file for application to an input of the shared datapath, and a demultiplexer operative to select an output of the shared datapath for application to an input of either the stack or the register file. A program executed by the processor selects one of the storage spaces using, for example, a tag bit associated with a given instruction and indicating which of the storage spaces is to be used with that instruction, or a branch machine view (bmv) instruction which generates a control signal operative to select the given one of the storage spaces.

Growing community of inventors

Bethlehem, PA, United States of America

Jesse Thilo