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La Telemecanique Electrique

Telemecanique Electrique

Jesse T Quatse

Jacky Pergent

Olivier Penot

Lionel Heitz

A programmable controller architecture utilizes specialized processors in a co-processing system so that each function is optimized. The system comprises first and second processors having respective instruction sets and respective associated means for fetching instructions from a common memory. Each of the processors and its instruction set is tailored to a corresponding processor's specialized function. Each processor's instruction set includes a subset of special instructions, the occurrence of one of which signifies that control is to be passed from one processor to the other. Upon encountering a special instruction within its special instruction subset, a given processor invokes associated control passing circuitry for suspending its own operation and commencing the operation of the other processor. The passage of control occurs very quickly so that the speed benefits of switching control are not lost in the overhead of such switching. Since passage of control renders one of the processors inactive, there is no requirement that the actual instructions of one processor be objectively distinguishable from those of the other.

Programmable controller ('PC') with co-processing architecture

An input/output device monitors the transmission of information between a processor of a programmable controller and sensors and actuators of a process to be controlled. This device includes electronic circuits adapted for calculating the parities of the digital words which pass therethrough, these parities being compared with corresponding parities calculated by the processor which thereafter invalidates the words having two different parities.

Error control apparatus using restore memory for recovering from parity

Method and apparatus for protecting and monitoring the transmission of

A very fast and efficient Boolean processor ('BP') (20) capable of compiling a full range of diagrams or expressions in ladder, logigram, and Boolean with a small but powerful instruction set. The BP includes an instruction decoder (34), combinatoric logic (35), a T-register (42) which holds the temporary results of a sequential AND operation, an N-register (43) which holds the initial Boolean value of T, a Binary Accumulator Memory ('BAM') (40) which is used as a scratchpad for a program which evaluates a ladder or logigram diagram or a Boolean expression, a source address ('S') in BAM (40) from which an initial operand is taken, a destination address ('D') in BAM (40) in which the result of an operation is stored, and a destination address register ('DAR') (45) in which the destination address is stored. The instruction set includes a subset of input instructions and a subset of structure instructions. The operand (I) of an input instruction is an address in IOIM (25). The operands (S,D) of a structure instruction are source and destination addresses in BAM (40). Each input instruction reads the value of a bit from IOIM and has the effect of logically combining this bit value with the value held in the T-register and possibly with the destination bit in BAM. The structure instructions cause operation on the pair of addresses S and D, and either describe the structure of the diagram to be compiled or permit the performance of logical functions between nodes in the diagram.

Boolean processor for a progammable controller

An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information between the CPU and its associated rack masters in serial fashion.

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Corte Madera, CA, United States of America

Jesse T Quatse