Nvidia Corporation

Jesse S Wang

Andreas J Gotterba

Lalit Gupta

Stefan P Sywyk

Jesse Yarbro Collins

Jason Golbus

Ka Yun Lee

Subhash Uppalapati

Kirk Twardowski

Mang Fu Matthew Wong

Chad Parsons

Karan Gupta

Sunghyun Song

Amy Chen

Federico Recio

Ramya Challa

The disclosure introduces a level-shifter including a boost circuit that provides a 'one-shot' pulse (a self-annihilating pulse) with the transitioning edge of the output signal. The pulse can be used to produce a faster output rise time and reduce the overall footprint of a level-shifter compared to conventional level-shifters. In one example the level-shifter includes: (1) input circuitry configured to receive one or more input signals from one or more input voltage domains, (2) output circuitry configured to provide an output signal, based on at least one of the one or more input signals, for an output voltage domain, wherein an operating voltage of the output voltage domain is greater than an operating voltage of the one or more input voltage domains, and (3) a boost circuit connected to the output circuitry and configured to provide a current pulse for a transition edge of the output signal.

Level-shifter having a wide operating range, a fast output fall delay and improved rise time

The disclosure provides improvements for transmitting data between different voltage domains of an IC, such as a chip. The disclosure introduces a data transfer circuit that uses a multi-voltage RAM, referred to herein as MVRAM, for transmitting data across the different voltage domains. The MVRAM has multiple memory cells with write ports and read ports on different clock and voltage domains. Accordingly, a write operation can occur completely on the write domain voltage and the read operation can occur completely on the read domain voltage. In one example, the data transfer circuit includes: (1) write logic operating at a first operating voltage, (2) read logic operating at second operating voltage, and (3) a MVRAM with write ports that operate under the first operating voltage and read ports that operate under the second operating voltage.

Multi-voltage RAM used to cross clock and voltage domains

A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

Keeper-free volatile memory system

To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.

Slew signal shaper circuit using two signal paths

A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

Area efficient memory cell read disturb mitigation

Systems and methods are described for implementing attribute aware, relationship-based access control by receiving a query to access a relational database from a user, determining if a rule of the relational database is applicable to the query, determining one or more relationships associated with the query based at least in part on the rule, and modifying the query by adding an extra join operation to the query based at least in part on the rule and the one or more relationships. Further, when a type of the rule is row level, a where clause filter is added to the modified query to enforce a condition of the rule, and when the type of the rule is field level, a case column is added to the modified query and a select clause is added to the modified query to wrap the query. The modified query is processed to produce a result.

Attribute aware relationship-based access control on row and field levels in a relational database

Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Three state latch

Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n&#x2212;1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation responsive to the completion. A completion of evaluation may not be aligned with a clock edge.

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Santa Clara, CA, United States of America

Jesse S Wang