Motorola Corporation

Burroughs, Inc.

Jesse R Wilson

Gary L Logsdon

Grady L Giles

Richard B Reis

Donald L Tietjen

Ralph C McGarity

Brent C Bolton

Terry V Hulett

Carl F Hagenmaier, Jr

R A Garibay, Jr

William C Moyer

James G Gay

Charles E Nuckolls

Carl P Pixley

Terry L Biggs

William D Atwell, Jr

Hyunwoo Cho

Joseph Carbonaro

Terry Van Hulett

Bernard F Plessier

A method (FIGS. 12-16) and a data processing system (FIG. 4) are used to verify the correct operation of one or more tri-state multiplexers (FIG. 3) located in a circuit model (37). The tri-state multiplexer checker (38) accesses the circuit model (37) and identifies the tri-state multiplexer(s). Once identified these tri-state multiplexers are checked to ensure that: (1) no two or more select/control lines to a tri-state MUX are enabled at a critical point in time wherein tri-state MUX output line contention can occur (i.e. both a logic zero and a logic one are being driven to the MUX output); and (2) that at least one select/control line is enabled during all critical periods of time so that a high impedance (high-Z) state is not propagated incorrectly through the MUX. This checking/verification is performed in a cut-set manner which is iterative and very time efficient when compared to prior methods.

Method and data processing system for verifying the correct operation of

A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the multiplexer (34). The phase lock loop circuit (32) receives its power from a power and control pin (22). The multiplexer (34) receives its power from a power pin (24). The power and control pin (22) is used as a control input to multiplexer (34). Multiplexer (34) uses the power and control pin (22) to select which input to output as a system clock.

Method and apparatus for providing both power and control by way of an

A data processor has an input synchronizer (10) which is dynamically enabled by a plurality of control signals provided by a user of the data processor. When the plurality of control signals has a predetermined logic level, a bias generator enable circuit (18) enables a bias generator (16). Subsequently, bias generator (16) enables a differential amplifier (12) to synchronize an asynchronous input signal to an operating frequency of the data processor. When the plurality of control signals does not have the predetermined logic level, bias generator enable circuit (18) disables bias generator (16). Subsequently, differential amplifier (12) is disabled and the asynchronous input is not synchronized with the internal operating frequency of the data processor. Therefore, because the user may choose the logic levels of each of the plurality of control signals, the user may dynamically disable input synchronizer (10) to minimize the power consumption of the data processor.

Data processing system having a dynamically enabled input synchronizer

A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.

Method and apparatus for shifting data in an array of storage elements

A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.

Toggle-free scan flip-flop

A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.

Binary magnitude comparator with asynchronous compare operation and

An integrated circuit is disclosed with a logic network having an output coupled to a sense node and having a virtual ground node, and with a sense amplifier having a sensing circuit coupled to the sense node to provide an output signal, charging and discharging feedback circuits coupled to the sense node that limit the swing of the sense amplifier, and an enable control to enable and disable the sense amplifer. In one embodiment in a CMOS integrated circuit a parallel network of n-channel transistors has an output connected to a sense node of a sense amplifier. A sensing inverter and a feedback inverter are connected to this sense node. The switchpoint of the feedback inverter is substantially higher than the switchpoint of the sensing inverter. A charging n-channel transistor is connected between the sense node and a power supply for charging the sense node, and the output of the feedback inverter is connected to the gate of the charging transistor. A discharging n-channel transistor is connected in series between the parallel network and ground. The gate of the discharging transistor is coupled to the sense node. The sense amplifier can enter a power-saving disable mode, and entry is controlled by a sense amplifier enable signal. This mode has two possible states corresponding to the state of the sense amplifier immediately preceding disablement and enables the sense amplifier to avoid output glitches when leaving the disabled mode. The sense amplifier uses two negative feedback loops, including the charging and discharging n-channel transistors, to limit the swing on the sense node, and this swing is substantially independent of the number of parallel transistors that are conductive.

Single-ended sense amplifier with dual feedback and a latching disable

A cache location selector selects locations in a cache for loading new information using either a valid chain, if not all locations already contain valid information, or a history loop otherwise. The valid chain selects the 'highest' location in the cache which does not already contain valid information. The history loop selects locations in accordance with a modified form of the First-In-Not-Used-First-Out (FINUFO) replacement scheme. Both the valid chain and the history loop are fully and efficiently implemented in hardware. During normal cache operation, both the valid chain and the history loop continuously seek an appropriate location to be used for the next load. As a result, that location is preselected well before the load is actually required.

FINUFO cache replacement method and apparatus

A content addressable memory (CAM) comprising a plurality of CAM cells, each including a static read/write memory (RWM) cell and an EXCLUSIVE OR (XOR) gate which couples a sense line to a ground line only if the logic state of the operand bit stored in the RWM cell does not match the logic state of an operand bit presented to the CAM cell. By arranging a selected subset of the CAM cells so that the XOR gates thereof act upon a first portion of either the sense line or the ground line while the balance of the CAM cells are arranged so that the XOR gates thereof act upon a second portion of that same line, a single coupler interposed between the first and second portions can be selectively disabled by a mask signal to simultaneously mask all of the bits stored in the subset of CAM cells during the matching operation of the CAM. If appropriate, the mask signal may comprise the bit stored in a particular one of the CAM cells.

Content addressable memory having field masking

Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.

Accelerated test apparatus and support logic for a content addressable

Disclosed is a selector switch for use in forming an asynchronous network of concurrent processors where the selector switch receives a message from one input port and transmits it to one of two output ports. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

Selector switch for a concurrent network of processors

Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

Arbiter switch for a concurrent network of processors

A four way selector switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

Four way selector switch for a five port module as a node asynchronous

A five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

Five port module as a node in an asynchronous speed independent network

A four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

Growing community of inventors

Austin, TX, United States of America

Jesse R Wilson