International Business Machines Corporation

Jesse Peter Surprise

Gerald Strevig, Iii

Shawn Kollesar

Chris Aaron Cavitt

Christopher J Berry

Michael H Wood

Adam P Matheny

Eduard Herkel

Jose Luis Neves

Ofer Geva

Stephen K Szulewski

Alexandra Echegaray

Eric A Foreman

Michael Kazda

Timothy A Schell

Florian Braun

Manuel Beck

Tsz-mei Ko

Brittany A Duffy

Marvin Von Der Ehe

Lukas Dällenbach

Chaobo Li

Bernd Kemmler

Heinz Josef Hemmes

Bernd Kemmier

Dina Hamid

Brandon Albert Bruen

Faisal Hasan

A hybrid block pinning optimization system includes a small-block processing module that processes a parent-level hierarchy including a plurality of child-level blocks and places a plurality of initial child-block pins corresponding to the child-level blocks. A child processing module places a logic element at a location within a given child block based on the placement of the initial child pins, discards the plurality of initial child pins while maintaining the location of the logic element, places at least one optimized child pin based at least in part on the location of the at least one logic element, and performs an abstraction operation on the logic element while maintaining the at least one child pin within the child blocks. A hierarchical large block synthesis (hLBS) processing module performs an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.

Approach to child block pinning

A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Even apportionment based on positive timing slack threshold

Aspects of the invention include a computer-implemented method of hierarchical large block synthesis (HLBS). At least a partial ring is created around an HLBS structure. The partial ring includes at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes. Certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic are identified. Decoupling capacitors of the relatively large sizes are disposed in the certain areas. A remainder of the areas of the HLBS structure are filled with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

Hierarchical large block synthesis (HLBS) filling

Embodiments of the invention are directed to a computer-implemented method of determining timing constraints of a first component-under-design (CUD). The computer-implemented method includes accessing, using a processor, a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs, wherein each of the plurality of timing constraint requirements is specifically designed for the CUD. The processor is used to perform a comparative analysis of each of the plurality of timing constraints to identify a single timing constraint that satisfies each of the plurality of timing constraints.

Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications

Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.

Clock gating latch placement

Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Metal fill shape removal from selected nets

Methods, systems and computer program products for providing cross-hierarchical block pin placement are provided. Aspects include designating potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block. Responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, aspects include placing pins at one or more of the potential pin placements. Aspects also include placing a set of pins based on aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.

Cross-hierarchical block pin placement

Methods, systems and computer program products for providing wire orientation-based latch shuddling are provided. Aspects include determining a classification of each latch of a plurality of latches as having a vertical orientation, a horizontal orientation or a mixed orientation. Aspects also include clustering the plurality of latches into one or more clusters based on the classifications of the plurality of latches. Each of the one or more clusters includes a unique set of latches of the plurality of latches. Aspects also include shuddling each of the one or more clusters around a local clock buffer within a layout. Each cluster of the one or more clusters is shuddled in a configuration around the local clock buffer based on the classifications of the corresponding unique set of latches of the plurality of latches.

Wire orientation-based latch shuddling

Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.

Local clock buffer controller placement and connectivity

A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Placement and timing aware wire tagging

A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design

A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Simulation of modifications to microprocessor design

Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

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Highland, NY, United States of America

Jesse Peter Surprise