International Business Machines Corporation

Jesse Ethan Craig

Stanley B Stanski

Scott T Vento

Sebastian Theodore Ventrone

Francis A Kampf

Jason Michael Norman

Suzanne Granato

John Sargis, Jr

Daneyand J Singley

Barbara L Powers

Deanna J Chou

Methods and systems initiate a simulation of an integrated circuit design. The simulation produces data that will exist in latches of the integrated circuit design when a device manufactured according to the integrated circuit design is operating. The methods and systems evaluate same-state latches associated with different portions of the simulation. If two of the same-state latches have the same state, given the same inputs and environmental conditions, the method and systems terminate a first portion of the simulation associated with a first of the same-state latches, but allow a second portion of the simulation associated with a second of the same-state latches to proceed.

Functional simulation redundancy reduction by state comparison and pruning

A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Chip lockout protection scheme for integrated circuit devices and insertion thereof

The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.

Verifying non-deterministic behavior of a design under test

A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Design structure for dynamically selecting compiled instructions

A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Method, apparatus and computer program product for dynamically selecting compiled instructions

A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately moveable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another.

Multi-arm disk drive system having interleaved read/write operations and method of controlling same

A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately movable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another.

A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is created for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.

Verification of the design of an integrated circuit background

A design verification method, comprising providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, M checkpointed splits, and N non-checkpointed splits; and executing the stimulus tree diagram, wherein said executing the stimulus tree diagram comprises, for i=1, . . . , M, executing an icheckpointed split of the M checkpointed splits, wherein said executing the icheckpointed split comprises (a) saving an icontext of an isimulation environment in which said executing the stimulus tree diagram is performed; and (b) after said saving the icontext is performed, executing from the icontext along Pi paths of the stimulus tree diagram branching from the icheckpointed split, wherein the icheckpointed split is a Pi-way split, Pi being an integer greater than 1.

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South Burlington, VT, United States of America

Jesse Ethan Craig