International Business Machines Corporation

Jesse Daniel Smith

Derick Gardner Behrends

Todd Alan Christensen

Travis Reynold Hebig

Daniel Mark Nelson

Anthony Gus Aipperspach

Chad Allen Adams

Peter Thomas Freiburger

Thinh V Luong

Louis Bernard Bushard

A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.

Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper

A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage.

Deep sleep wakeup of multi-bank memory

A static random access memory with write-through capability includes a memory cell configured to store a bit of data. A write enable signal is configured to enable writing a write value from a write line input into the static random access memory cell and to enable reading a read value from the memory cell onto a DOT line. A local evaluation circuit is configured to place the write value from the write line onto the DOT line during a single clock cycle in which the value is being written into the memory cell. An early read suppression circuit is configured to electrically isolate the DOT line from a data out line thereby preventing a leakage current loss from the local evaluation circuit and is also configured to make the value placed on the DOT line to be read from the data out line during the single clock cycle.

Method for selectable guaranteed write-through with early read suppression

A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report.

Assessing resources required to complete a VLSI design

A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.

Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic

An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.

Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels

A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

Implementing enhanced LBIST testing of paths including arrays

Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.

Low power level shifting latch circuits with gated feedback for high speed integrated circuits

A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.

Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability

A method for passing data from an input to an output of a domino read access path in domino read SRAM memory including receiving at least a portion of the input data from a latch configuration, gating a global precharge signal, gating a bit select circuitry signal, driving the input data statically through a transmission gate of a static bypass multiplexer to the global dot of the domino read SRAM memory, initiating a write around cycle signal, offsetting the write around signal input into the static bypass multiplexer and the precharge signal by at least one phase using a wave shaper, driving the input data from the global dot through a keeper circuit, and driving the input data from the keeper circuit to at least one NAND gate of a pair of cross-coupled NAND gates, the pair of cross-coupled NAND gates being configured in a transparent state.

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Rochester, MN, United States of America

Jesse Daniel Smith