Intel Corporation

Jesse C Brandeburg

Patrick L Connor

John Ronciak

Prafulla Deuskar

Christopher Leech

Scott P Dubal

Parthasarathy Sarangam

Stephen T Palermo

Anjali Singhai Jain

Anil Vasudevan

Eliezer Tamir

Trevor Cooper

Kapil Sood

Jr-Shian Tsai

Iosif Gasparakis

Donald Wood

Mitu Aggarwal

Pradeepsunder Ganesh

Mitchell A Williams

Mike Bursell

Andrew J Herdrich

Thomas E Willis

Michael Hingston McLaughlin Bursell

Linden Cornett

Ilango S Ganga

Edwin Verplanke

David E Cohen

Parthasarathy Sangam

Techniques for providing adaptive virtual function (VF) drivers capable of operating with physical devices having a plurality of different hardware configurations are described. In one embodiment, for example, an apparatus may include logic to implement a virtual machine (VM), the logic to initialize an adaptive virtual function (VF) driver to facilitate communication between the VM and a physical device to be virtualized, establish communication between the adaptive VF driver and a physical function (PF) driver of the hypervisor for the physical device, activate a standard feature set for the adaptive VF driver to execute on a PF of the physical device, and negotiate activation of an advanced feature set for the adaptive VF driver to execute on the PF, the adaptive VF driver to provide the advanced feature set to the PF, the PF activate each feature of the advanced feature set supported by the PF.

Adaptive virtual function drivers for electronic devices

Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Packet processing with reduced latency

Examples described herein can be used to allocate replacement receive buffers for use by a network interface, switch, or accelerator. Multiple refill queues can be used to receive identifications of available receive buffers. A refill processor can select one or more identifications from a refill queue and allocate the identifications to a buffer queue. None of the refill queues is locked from receiving identifications of available receive buffers but merely one of the refill buffers is accessed at a time to provide identifications of available receive buffers. Identifications of available receive buffers from the buffer queue are provide to the network interface, switch, or accelerator to store content of received packets.

Receive buffer management

Technologies for monitoring service level agreement (SLA) performance in an end-to-end SLA monitoring architecture include a network functions virtualization (NFV) SLA controller configured to manage SLA agents initialized in various network processing components of the end-to-end SLA monitoring architecture. To do so, the NFV SLA controller is configured to provide instruction to the SLA agents indicating which types of telemetry data to monitor and receive the requested telemetry data, as securely collected and securely packaged by the SLA agents. The NFV SLA controller is further configured to securely analyze the received telemetry data to determine one or more performance metrics and compare performance benchmarks against the performance metrics to generate an SLA report that includes the results of the comparison. Other embodiments are described and claimed.

Technologies for independent service level agreement monitoring

Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache 'fast-path' forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.

Method and apparatus for accelerating VM-to-VM network traffic using CPU cache

The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a 'super' virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.

Enhanced virtual function capabilities in a virtualized network environment

Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.

Methods and apparatus for multi-stage VM virtual network function and virtual service function chain acceleration for NFV and needs-based hardware acceleration

Technologies for pacing transmission of network packets by a computing device to a remote computing device include performing a segmentation offload operation to segment a payload of a network packet into a plurality of network packet segments in response to a determination that a size of the payload is greater than a maximum allowable payload size. The computing device additionally determines a packet pacing interval and transmits the plurality of network packet segments to the remote computing device at a transmission rate based on the packet pacing interval.

Technologies for network packet pacing during segmentation operations

In general, in one aspect, the disclosure describes a method includes accessing data of an egress packet belonging to a flow, storing data associating the flow with at least one queue based on a source of the data of the egress packet. The method also includes accessing an ingress packet belonging to the flow, performing a lookup of the at least one queue associated with the flow, and enqueueing data of the ingress packet to the at least one queue associated with the flow.

Growing community of inventors

Portland, OR, United States of America

Jesse C Brandeburg