Linear Technology Corporation

Analog Devices,inc.

Analog Devices International Unlimited Company

Jesper Steensgaard-Madsen

Andrew Joseph Thomas

Hongxing Li

Christopher Peter Hurrell

Florin Alexandru Oprescu

Alfio Zanchi

David M Thomas

Sanjay Rajasekhar

Joseph L Sousa

Micah Galletta O'Halloran

Raymond Thomas Perry

Manideep Gande

Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

Low-noise switched-capacitor circuit

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

Analog-to-digital conversion circuit with improved linearity

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Analog-to-digital converter with auto-zeroing residue amplification circuit

Analog-to-digital converter (ADC) circuitry to convert an analog signal to a digital signal is disclosed herein. The ADC circuitry can utilize pipelined-interpolation analog-to-digital converters (PIADCs) with adaptation circuitry to correct regenerative amplification cells of the PIADCs. The PIADCs can implement a rotational shuffling scheme for correction of the regenerative amplification cells, where the correction implemented by the regenerative amplification cells allows for offsetting of latches of the regenerative amplification cells.

Pipelined-interpolating analog-to-digital converter

Noise sources in an ADC circuit can include kT/C noise of a sampling capacitor, noise coupling on to sampling capacitors from digital circuits, and amplifier noise. Also, charge injection from mismatch in sample switches can cause offsets. These various noise sources can be largely canceled or reduced using described techniques. As a result, the size of the sampling capacitors can be greatly reduced, while still achieving significantly improved noise performance and power efficiency for the overall converter.

Low noise analog-to-digital converter

Various background calibration techniques to calibrate inter-stage gain, e.g., in pipelined ADCs, are described to allow open loop amplifier circuits to be used as residue amplifiers for better power efficiency. Using various techniques, a well-controlled perturbation can be injected between two conversions and the actual perturbation after a residue amplifier can be measured. By comparing the actual measurement against an expected value, the gain information of the residue amplifier can be estimated and then calibration can be applied.

Inter-stage gain calibration in double conversion analog-to-digital converter

A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal.

Configuring signal-processing systems

An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

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San Jose, CA, United States of America

Jesper Steensgaard-Madsen