Intel Corporation

Jerzy B Kolinski

Stephen S Pawlowski

Peter D MacWilliams

Gary A Solomon

Albert Rudy Nelson

John Thomas Sprietsma

Henry Schaechterle

A computer includes a dual mode power supply that includes a main voltage converter and a standby voltage converter. The main voltage converter generates a main operating voltage at a normal operating current. The standby voltage generator generates a standby voltage at a standby current. The power supply outputs a dual mode output that includes both the main voltage and the standby voltage. The standby current is less than the normal operating current. The computer includes a host processor, a memory array, and a wake-up device. A power management device is coupled to the host processor and receives at least the standby voltage. The dual mode output from the power supply is input to the wake-up device and the memory array to allow the computer to be placed in a power saving mode by terminating supply of the main voltage. While in the power saving mode and receiving only the standby voltage, the wake-up device can wake-up the computer.

Computer having a dual mode power supply for implementing a power saving

An equal length symmetric computer bus topology. The equal length symmetric computer bus topology provides a bus signal path to a number of bus nodes. Each bus signal path extends from each node on the computer bus to a central junction point. The bus signal paths are of equal length and have identical electrical characteristics. The equal length symmetric computer bus topology minimizes the effect of transmission line reflections upon the bus signals. The equal length symmetric computer bus topology also causes very little clock skew.

Equal length symmetric computer bus topology

An asynchronous computer bus providing transfers of data on consecutive processor clock cycles. The bus comprises consecutive data transfer commence indication means, starting address transmission means, consecutive data transfer indication means, and data transmission means. The invention provides for the 'burst' capabilities of modern processors wherein entire blocks of data are transmitted within a single request.

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Portland, OR, United States of America

Jerzy B Kolinski