Maxim Integrated Products, Inc.

Lsi Logic Corporation

Symbios, Inc.

Symbios Logic Inc.

Jerzy Antoni Teterwak

Paul W Kalthoff

Dan McMahill

Joseph Lutsky

Daniel E Ballare

A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

Transmitting clock reference over reverse channel in a bidirectional serial link

A capacitive sensing system are configured to sense a capacitance value and convert the sensed capacitance value to a digital format. The capacitive sensing system provides good selectivity and immunity to noise and interference, which can be further enhanced by enabling spread spectrum excitation. In some embodiments, the capacitive sensing system utilizes a sinusoidal excitation signal that results in low electromagnetic emissions, limited to narrow frequency band. In some embodiments, the capacitive sensing system is configured to operate in a spread spectrum mode, in which the majority of the excitation signal power is carried in the assigned bandwidth. The excitation frequency and the bandwidth of the spread spectrum excitation signal are programmable in a wide range, which allows for avoiding frequency conflicts in the operating environment.

Method and apparatus for sensing capacitance value and converting it into digital format

A system includes a clock interconnect network having an input node and a plurality of output nodes. The clock interconnect network receives a clock input at the input node and distributes, based on the clock input, a plurality of clock signals via respective ones of the plurality of output nodes. A propagation delay of each of the plurality of clock signals distributed by the clock interconnect network is approximately equal to respective propagation delays of others of the plurality of clock signals distributed by the clock interconnect network. A digital-to-analog converter includes a plurality of segments, each outputting a respective output, and a plurality of drivers. Each of the plurality of drivers receives a respective one of the plurality of clock signals and provides a driver signal to a respective one of the plurality of segments based on the respective one of the plurality of clock signals.

Interconnect structures for minimizing clock and output timing skews in a high speed current steering DAC

A digital-to-analog converter (DAC) system includes a DAC and a clock interconnect module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals. Each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals. The clock interconnect module includes an interconnect loop. A clock input is connected to a first portion of the interconnect loop and the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers. An output interconnect module receives the positive outputs and the negative outputs generates a differential output signal.

A digital-to-analog converter (DAC) system includes a DAC and a current trimming module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers, receives segment currents from a respective one of a plurality of segment current sources, and generates an output current based on the driver signals and the segment currents. The current trimming module stores a plurality of trim coefficients and adjusts respective threshold voltages associated with the plurality of segment current sources based on the plurality of trim coefficients.

Method for trimming segment currents in current steering DAC based on most back gate voltage modulation

A system includes a digital to analog converter, a power amplifier, an analog-to-digital converter, a filter, and a pre-distortion module. The digital to analog converter generates analog data based on digital data. The power amplifier generates output data based on the analog data. The analog-to-digital converter generates samples based on the output data at a sampling rate less than a Nyquist sampling rate. The filter filters the digital data and generates filtered data. The pre-distortion module distorts the digital data based on the samples and the filtered data to compensate for distortion generated by the power amplifier.

Digital pre-distortion system for radio frequency transmitters with reduced sampling rate in observation loop

A digital to analog converter includes a first switch, a second switch, and a driver module. The first switch includes a first differential pair of transistors connected to first inputs to receive digital data for conversion to analog data based on a clock signal output by a clock, and first outputs to output the analog data. The second switch includes second and third differential pairs of transistors connected to second inputs and the first outputs. The driver module drives one of the second inputs based on the digital data and toggles the second switch during a first cycle of the clock signal if the first switch is not toggled during the first cycle of the clock signal.

Current-steering digital-to-analog converter with cancellation of dynamic distortion

A digital-to-analog converter (DAC) includes, in a segment of the DAC, a first switch and a second switch. The first switch includes a first pair of transistors having a first set of inputs and has a first output connected to an output of the DAC. The second switch includes second and third pairs of transistors having second and third sets of inputs, respectively, and has a second output that is connected to the output of the DAC. A driver module generates control signals to drive the first, second, and third sets of inputs based on data received by the DAC for conversion from digital to analog format at a conversion rate determined by a clock. The control signals toggle one of the first and second switches during each cycle of the clock.

An apparatus and method for reducing distortion from an output of a digital-to-analog converter (DAC). In one implementation, the distortion being reduced is third order harmonic distortion caused by charge transfer effects and instantaneous output impedance drop during switching. Each of the embodiments includes a module adapted to generate a distortion correction signal being a function of the input digital signal, the full scale code of the DAC, the load resistance, the conversion rate of the DAC, and a proportionality constant. In another implementation, the distortion being reduced is higher order harmonic distortion caused by timing skew between a main DAC and a least significant bit (LSB) DAC. Each of the embodiments includes a module adapted to generate a distortion correction signal being a function of the input digital signal, the number of levels covered by the LSB DAC, the conversion rate of the DAC, and the timing skew.

System and method for improving the dynamic performance of a digital-to-analog converter (DAC)

A current steering digital-to-analog (DAC) having improved dynamic performance and output signal quality (i.e. improved SFDR characteristic). The DAC includes current steering segments each having differential transistors to steer a current from a summing node to either the positive or negative output. The DAC further comprises a control circuit to reduce the variation of the voltage present at each summing node. More specifically, the control circuit includes a first circuit that controls the threshold voltage of the corresponding differential transistors that are electrically connected to the positive output in response to the sensed positive output voltage such that the voltages at the corresponding summing nodes remain constant. Similarly, the control circuit includes a second circuit that controls the threshold voltage of the differential transistors that are electrically connected to the negative output in response to the sensed negative output voltage such that the voltages of the corresponding summing nodes remain constant.

Current steering digital-to-analog (DAC) converter with improved dynamic performance

A high Q tank circuit is employed at the output of a digital, crystal controlled oscillator to generate a high voltage amplitude signal. The tank circuit has a resonant frequency greater than the maximum required oscillation frequency. During each oscillation cycle, oscillation within the tank circuit is stopped in an energy efficient manner such that the resonant oscillation period is extended to match the required oscillation period. Modulation of the digital oscillator signal appears in the output circuit signal.

High voltage crystal controlled oscillator for an electronic pen used with an electrostatic digitizing tablet

A flat panel display is coupled with an electrostatic stylus driven digitizing panel to produce a display and digitizer system having an interference control feature. The interference control feature first determines the operating frequency of the flat panel display and/or the operating frequency of the stylus. The interference controller may then incrementally reduce the operating frequency of the flat panel display and/or the operating frequency of the stylus until the operating frequency causing the least interference is ascertained. Once the operating frequency causing the least interference is ascertained the interference controller selects new operating parameters for the display and digitizer system.

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Colorado Springs, CO, United States of America

Jerzy Antoni Teterwak