Ciena Corporation

Jerry Yee-Tung Lam

Naim Ben-Hamida

Sadok Aouini

Mohammad Honarparvar

Soheyl Ziabakhsh Shalmani

Douglas Stuart McPherson

Robert G Gibbins

Jacob Pike

Marinette Besson

David Berton

Matthew Baby Varghese

Euhan Chong

A transceiver includes a first transmit (Tx) component configured to connect to a second receive (Rx) component in a second transceiver; a first Rx component configured to connect to a second Tx component in the second transceiver; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to continuously calibrate a first Look-Up Table (LUT) configured to feed operating codes to a first phase rotator connected to an output of the single PLL circuit and to one of the first Tx component and the first Rx component. In an embodiment, the control circuit is further configured to continuously calibrate a second LUT configured to feed operating codes to a second phase rotator connected to an output of a single PLL circuit in the second transceiver.

Reducing non-linearities of a phase rotator

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

Digitally enhanced digital-to-analog converter resolution

Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

Apparatus and method for wideband multi-phase clock generation

Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A card include first transmit (Tx) component configured to connect to a second receive (Rx) component in a second card; a first Rx component configured to connect to a second Tx component in the second card; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to compensate for differences between i) the first Tx component and the second Rx component, and ii) the first Rx component and the second Tx component.

Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.

Multiple clock domain alignment circuit

Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A circuit, according to one implementation, includes a single Phase-Locked Loop (PLL) circuit having a main path and a return path forming a feedback loop. The circuit also includes one or more phase rotators connected to an output of the single PLL circuit outside the feedback loop and one or more adaptable Look-Up Tables (LUTs) populated with operating code to be provided to the one or more phase rotators for defining operating characteristics of the one or more phase rotators. Furthermore, the circuit includes a control device configured to receive phase response characteristics from the one or more phase rotators. The control device is further configured to modify the operating code of the one or more adaptable LUTs based on the phase response characteristics to reduce non-linearities of the one or more phase rotators.

A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*&#x394;t, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.

Phase skipping technique for high-speed, high-phase number delay locked loop

Described herein are apparatus and methods for highly linear phase rotators with continuous rotation. A method includes generating a first code and a second code based on a desired offset to match a first and second frequency, respectively, calibrating the first code and the second code based on first phase rotator characteristics and second phase rotator characteristics, respectively, generating first N phase offset codes and second N phase offset codes from a calibrated first and second code, respectively, wherein each phase offset code constrains functionality of the first phase rotator and the second phase rotator, respectively, associated with a phase of the input clock to a defined region of operation, rotating a clock using the first N phase offset codes and the second N phase offset codes to match the first and second frequency, respectively.

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Stittsville, Canada

Jerry Yee-Tung Lam