L-3 Communications Integrated Systems L.p.

L-3 Communications Corporation

L-3 Integrated Systems Company

Spirit Aerosystems, Inc.

Jerry William Yancey

Yea Zong Kuo

Matthew Pascal DeLaquil

Deepak Prasanna

Antone Lee Kusmanoff

Timothy M Adams

Mathew A Sanford

Aya N Bennett

A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit. The interpolator inserts a desired number of zeros into the time-sampled data stream to adjust the time-sampled data stream to an increasing sampling rate. The control unit controls the settings of the crosspoint switch, the arithmetic unit, and the multiply accumulate unit. The output formatter combines the in-phase sum of products and the quadrature sum of products to create a filtered complex-number discrete-time sample.

Method and apparatus for a finite impulse response filter

A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.

Reconfigurable networked processing elements partial differential equations system

Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same ASIC device.

Heterogeneous computer architecture based on partial reconfiguration

A programmable element for data processing comprises a crosspoint switch (), a mathematical operation module (), and a plurality of data hold modules (). Each of the data hold modules () receives data from the crosspoint switch () and communicates the data to an input of the mathematical operation module () such that data arrives at the inputs of the mathematical operation module () substantially simultaneously. A first data hold module () communicates a first data valid signal to a second data hold module () upon receipt of first valid data, and the second data hold module communicates a second data valid signal to the first data hold module upon receipt of second valid data. The first data hold module () communicates the first valid data to a first input upon receipt of the first valid data and the second data valid signal, and the second data hold module () communicates the second valid data to a second input upon receipt of the second valid data and the first data valid signal.

Datapipe synchronization device

Provided is a method and system for noise-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the minimum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals less than the minimum pulse interval to record a set of minimum signal values. The incoming signal is also sampled a predetermined number of times at intervals less than the minimum pulse interval to record a set of maximum signal values. At least the first greatest value from the set of maximum signal values is discarded. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values. The method is repetitive, continually re-determining the threshold values so as to adapt to changes in the incoming signal. A system for performing the method is also provided.

Noise-driven recovery of a digital pulse stream

Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Reconfigurable communications infrastructure for ASIC networks

Provided is a programmable matrix element or 'PME' (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in 'datapipe' fashion, which is to say via a specified number of parallel data pathways.

CPU datapipe architecture with crosspoint switch

An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory element to selectively operate in one of a plurality of modes. In a first mode, the memory element communicates stored data to the output port upon receiving the control signal; in a second mode the memory element communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element stores a second data value consisting of at least a portion of each of two separate input values received at the input port. Each programmable element may write data to and read data from a memory element of any of the other programmable elements.

Reading and writing a memory element within a programmable processing element in a plurality of modes

A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register.

Linear combiner weight memory

One or more nodes of a network may be configured to provide substitute header information for insertion into a received data packet and then to retransmit the data packet with the modified header information to other network destinations. One or more other downstream nodes may be configured to do likewise, thus allowing a packet to proceed through a selected number of multiple destinations in the network without being shortened, and so that the number of control words required in each packet is reduced, in increasing data bandwidth for the network.

Methods and systems for relaying data packets

Provided is a digital signal processing device, specifically a modular application specific integrated circuit ('ASIC'), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing.

Modular ASIC with crosspoint switch

An apparatus operable to interface an electronic component with a signal input. The apparatus may generally include a low-ohm resistor and a voltage translator coupled with the low-ohm resistor. The low-ohm resistor is operable to couple with the input to receive an input signal therefrom. The voltage translator is operable to couple with the electronic component and translate the input signal from a first voltage to a second voltage for use by the electronic component. The low-ohm resistor and voltage translator may be positioned by a pick and place assembly machine such that embodiments of the present invention do not require a technician to manually couple and solder the apparatus to the input and electronic component.

Method and apparatus for interfacing components

A system for data processing comprises a host circuit () and an integrated circuit (), the host circuit () being external to the integrated circuit (). The integrated circuit () includes a plurality of programming elements (), each element () including a host interface () for receiving data and a first control signal from the host circuit (), a control interface () for receiving a second control signal. Each element () includes a crosspoint switch (), and a register array () for receiving and storing data from the crosspoint switch () according to the first and second control signals, for receiving and storing data from the host interface () according to the first and second control signals, and for communicating stored data to the crosspoint switch () according to the first and second control signals.

Datapipe CPU register array

Provided is a method and system for signal-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the maximum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals greater than the maximum pulse interval to record a set of minimum signal values and a set of maximum signal values. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values. The method is repetitive, continually re-determining the threshold values so as to adapt to changes in the incoming signal. A system for performing the method is also provided.

Signal-driven recovery of a digital pulse stream

Application Specific Integrated Circuit ('ASIC') devices, such as Field Programmable Gate Arrays ('FPGAs'), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (&#x201c;MGT&#x201d;) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (&#x201c;RHA&#x201d;) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

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Rockwall, TX, United States of America

Jerry William Yancey