Raytheon Company

Jerry W Drake

Kersi F Cooper

Bruce G Armstrong

Jok Y Go

Gerard J Shaw

Peter J Portesi

Jay H Chun

A memory cell comprising a memory region of amorphous silicon, such memory region having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical programming signal applied thereto. The memory region is disposed over a metal Schottky contact, such as platinum-silicide (PtSi), formed in a support body. A first barrier layer comprising a refractory metal such as titanium-tungsten (TiW) is disposed between the memory region and Schottky contact. A first input terminal comprising a metal strip conductor, such as aluminum, is disposed over the memory region, with a second refractory metal barrier layer being disposed between the memory region and metal strip conductor. A second input terminal is disposed within the support body. With such arrangement, the material of the Schottky contact (PtSi) is substantially prevented from migrating or diffusing into the silicon memory region upon application of the electrical programming signal between the first and second input terminals, thereby preserving the structure of the metal contact and maintaining a low reverse bias leakage current for a Schottky diode comprising such metal contact. Also, the level of the programming signal may be increased, providing more complete programming of the memory region to the second, electrically conductive state.

Programmable memory cell structure including a refractory metal barrier

A programmable memory element for a programmable read only memory. The programmable memory element includes a Nichrome fusible link with a first metallization layer formed in contact with the Nichrome fusible link. An insulating layer is formed over the first metallization layer and over a portion of the Nichrome. The insulating layer is formed by first chemically vapor depositing a relatively thin layer of silicon dioxide at atmospheric pressure and then chemically vapor depositing a thicker layer of silicon nitride over the thin silicon dioxide layer, such silicon nitride layer being chemically vapor deposited in a vacuum.

Programmable read only memory

A programmable memory element for a programmable read only memory. The programmable memory element includes a nichrome fusible link with a first metallization layer formed in contact with the nichrome fusible link. An insulating layer is formed over the first metallization layer and over a portion of the nichrome. The insulating layer is formed by first chemically vapor depositing a relatively thin layer of silicon dioxide at atmospheric pressure and then chemically vapor depositing a thicker layer of silicon nitride over the thin silicon dioxide layer, such silicon nitride layer being chemically vapor deposited in a vacuum. The layer of silicon dioxide is thin enough so that any cusps formed around the corners of the first metallization layer are relatively small. The deposition of the silicon dioxide layer is performed at atmospheric pressure and allows the silicon dioxide to provide moisture protection to the nichrome. The later deposited silicon nitride layer has sufficient thickness to provide the desired electrical insulation between a second metallization layer and the first metallization layer and the thin silicon dioxide layer provides a barrier to the silicon nitride layer so that the silicon nitride layer will not effect the resistivity of the fusible link. A via is formed in the silicon nitride layer and the underlying silicon dioxide layer to expose a portion of the first metallization layer. The second metallization layer is then deposited over the insulating layer and through the via onto the exposed portion of the first metallization layer.

A semiconductor integrated circuit structure wherein a first metal interconnecting system is formed on a semiconductor body having active and/or passive elements formed therein. An insulating layer is deposited on the first metal interconnecting system. Apertures are formed in selected regions of such layer and are cleaned in a sealed sputtering chamber. A refractory metal is deposited over the insulating layer and through the apertures onto the first metal interconnecting system in a sealed sputtering chamber. A lead metal is deposited over the refractory metal layer. Selected portions of such refractory metal and lead metal are removed to form a second metal interconnecting system. With such structure and method the surfaces of the first metal interconnecting system which are to be connected to a second metal interconnecting system through the apertures are cleaned of oxides and other contaminates in a sealed sputtering chamber and are then sealed from further contamination by the refractory metal layer. The structure and method improves the electromigration resistance of the second metal interconnecting system because of the presence of the refractory metal layer. Further, the refractory metal layer acts as a barrier layer which prohibits interdiffusion between the connected portions of the first and second interconnecting systems. The assurance of good ohmic contact between the connected portions of the interconnecting systems reduces the surface area required for metalization.

Growing community of inventors

Los Gatos, CA, United States of America

Jerry W Drake