Texas Instruments Corporation

Jerry R Vanaken

Karl M Guttag

Raymond Pinkham

Donald J Redwine

Mark F Novak

Andrew L Heilveil

Fredrick A Valente

In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.

Video display system using memory with parallel and serial access

A semiconductor memory circuit includes memory arrays (10), (12), (14) and (16). Each of the memory arrays has associated therewith shift registers (34), (36), (38) and (40). Transfer gates (54) are disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shift clock signal to serially output data therefrom. A delay circuit (292) is provided for delaying shifting of data for a predetermined duration to ensure that a complete transfer of data has been effected. Transfer of data is inhibited until the occurrence of the XBOOT signal by circuit (296) to provide for early occurrence of the transfer signal. Data access is maintained by a delay circuit (330) to accommodate late occurrence of the transfer signal by delaying the internal row address strobe.

Video serial accessed memory with midline load

In a computer system, an improved memory circuit is provided for accomodating video display circuits with CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accomodate any CRT screen intended to be used, and it further includes a serial shift register having a plurality of taps at locations corresponding to different preselected columns of cells in the chip. In the system, provision is included for selecting taps to unload only the portion of the shift register containing the bits of interest, whereby unused portions of the chip may be effectively excluded and the time for transferring data of interest to the CRT screen is reduced.

A single-chip microprocessor device of the MOS/LSI type contains an ALU, internal busses, address/data registers, an instruction register, and control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by control lines and a bidirectional multiplexed address/data bus. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM not in the main off-chip memory map) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from 'native' instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.

Growing community of inventors

Houston, TX, United States of America

Jerry R Vanaken