Texas Instruments Corporation

Jerry R Van Aken

Karl M Guttag

Michael D Asal

Neil Tebbutt

Mark F Novak

Carrell R Killebrew, Jr

Richard D Simpson

Jeffrey L Nye

Thomas A Dye

Sydney W Poland

Derek Roskell

Chenwei J Yin

William Robert Krenik

Michael A Denio

Henry T Yung

Louis J Izzi

James G Littleton

Robert C Thaden

Jeffrey C Bond

William S Egr

Douglas C Crawford

Mike Asal

Graham Short

David W Gulley

Rudy Albachten

A palette device controllable by a digital computer with a video memory to produce signals representing color for a video monitor. The palette device includes a multiple-bit input latch for entry of color codes from the video memory, and a look-up table memory for supplying color data words in response to color codes from the input latch. A digital to analog converter responds to color data words to produce an analog color signal. Selection circuitry connected to the input latch and to the look-up table memory supplies the digital to analog converter either with a color data word supplied by the look-up table memory or with a color data word comprised of color codes from the input latch. Improved graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.

Palette devices, systems and methods for true color mode

The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may by simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.

Process of processing graphics data

This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to '0'. Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is '1'. If the difference is less than zero, then the next quotient bit is '0'. The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are '0'. Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.

Iterative division apparatus, system and method employing left most

An iterative technique for division having a divisor of N bits and a numerator of more than N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator is left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. Next the divisor is subtracted from the N most significant bits of the numerator. If the difference is greater than or equal to zero, then the next quotient bit is '1' and the difference is substituted for the N most significant bits of the numerator. If the difference is less than zero, then the next quotient bit is '0'. Then the numerator is left shifted one place. These iterations repeat until they exceed N. The last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are '0'.

A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the n.sup.th first AND gate 126 coupled to the n.sup.th one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an n.sup.th one of the second AND gates 128 coupled to a (j-n+1).sup.th one of the first input terminals, the second input ports of the second AND gates 128 are coupled to a second control. An array of j sequentially ordered OR gates 130 are provided each having first and second input ports and an output port, the first input port of an m.sup.th one of the OR gates 130 being coupled to the output of an m.sup.th one of the first AND gate 126, the second input port of an n.sup.th one of the OR gates 130 coupled to the output of the n.sup.th one of the second AND gates 128. Wherein j is a consonant, n is a variable between 1 and j, and m is a variable between 1 and j.

Flexible graphics interface device switch selectable big and little

The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented or decremented. This instruction serves to enhance the speed at which a line or computed curve may be drawn in the bit mapped display.

Graphics computer system, a graphics system arrangement, a display

An apparatus and method for filling regions bounded by piecewise-conic curves and more particularly to such an apparatus and method which is directed to curves defined by a conic equation. This simplifies the process of generating filled contours in applications, such as printing, which are based on font outlines while at the same time reducing computer time and generating more accurate results for each curve generation.

Apparatus and method for filling regions bounded by conic curves

A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.

Video interface palette, systems and method

A palette device controllable by a digital computer with a video memory having a bus for supplying multiple color codes for the palette device in each bus cycle. The palette device includes a multiple-bit input for entry of the color codes from the bus, and a look-up table memory for supplying color data words in response to the color codes from the input. Color code transfer circuitry is connected between the input and the look-up table memory to supply the look-up table memory from the input sequentially with color codes of selectable width packing the entire width of the bus. Improved palette devices, graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.

Packed bus selection of multiple pixel depths in palette devices,

The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.

Graphics data processing apparatus with draw and advance operation

An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.

Graphics systems, palettes and methods with combined video and shift

An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.

Multiprocessor software interface for a graphics processor subsystem

A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.

Data processing apparatus with self-emulation capability

The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to enhance the speed at which a line or computed curve may by drawn in the bit mapped display.

Growing community of inventors

Sugar Land, TX, United States of America

Jerry R Van Aken