Micron Technology Incorporated

Round Rock Research, LLC

Other

Jerry Michael Brooks

David J Corisis

Larry Duane Kinsman

Jerrold L King

Walter L Moden

Terry R Lee

Matt E Schwab

Warren M Farnworth

Salman Akram

Timothy J Allen

Aaron M Schoenfeld

Tracy V Reynolds

Leonard E Mess

S Derek Hinkle

Steven G Thummel

Chad A Cobbley

Robert William Courtenay

George P McGill

Syed Sajid Ahmad

Chender Huang

Jerold L King

A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.

Integrated circuit package having reduced interconnects

A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.

Stackable ball grid array package

A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.

Multi-chip module and methods

A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Semiconductor device and method of fabrication thereof

A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangements, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high-density low-profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Semiconductor device assemblies, electronic devices including the same and assembly methods

A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device.

Semiconductor devices including semiconductor dice in laterally offset stacked arrangement

A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.

Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies including the rerouted semiconductor devices

A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Vertical surface mount assembly and methods

A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Method of forming a semiconductor device

Methods of forming an integrated circuit package

A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.

A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The stacked multiple offset chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Stacked mass storage flash memory package

A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assembly. The conductive traces may be carried upon a single surface of the routing element substrate, be carried internally by the routing element substrate, or include externally and internally carried portions. The routing element may also include a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multichip module. Multichip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

Growing community of inventors

Caldwell, ID, United States of America

Jerry Michael Brooks