Other

Telcom Semiconductor, Inc.

Microchip Technology Inc.

Ancestry.com Operations Inc.

Hybrid Systems Limited

The Generations Network, Inc.

Jerry M Collings

Ali Tasdighi Far

Daren Thayne

Ali Tasdighi

Michael J Wolfgramm

Kendall J Jefferson

James Mark Hamilton

Bennett Cookson, Jr

Ken Boyer

Grant Parkinson

Douglas T Reid

Donald E Alfano

Vincent Quiquempoix

Joseph James Judkins

Quoi V Huynh

Sang Ton Ngo

Gabriele Bellini

Chuong Nguyen

Digital approximate multipliers (aMULT) utilizing interpolative apparatuses, circuits, and methods are described in this disclosure. The disclosed aMULT interpolative methods can be arranged or programmed to operate asynchronously and or synchronously. For applications where less precision is acceptable, fewer interpolations can yield less precise multiplication results, while such approximate multiplication can be computed faster and at lower power consumption. Conversely, for applications where higher precision is required, more interpolations can generate more precise multiplication results. As such, by utilizing the disclosed aMULT method, the resolution and precision objectives of an approximate multiplication function can be pre-programmed or adjusted real-time and or on the fly, which enables optimizing for different and flexible power consumption and speed of multiplication, in addition to enabling the optimization of an approximate multiplier's die size and cost in accordance with cost-performance objectives.

Digital approximate multipliers for machine learning and artificial intelligence applications

Digital approximate squarer (aSQR)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed aSQR methods can operate asynchronously and or synchronously. For applications where low precisions is acceptable, fewer interpolations can yield less precise square approximation, which can be computed faster and with lower power consumption. Conversely, for applications where higher precision are required, more interpolations steps can generate more precise square approximation. By utilizing the disclosed aSQR method, precision objectives of a squarer approximation function can be programmed real-time and on the fly, which enables optimizing for power consumption and speed of squaring, in addition to optimize for the approximate squarer's die size and cost.

Digital approximate squarer for machine learning

Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.

Glitch free current mode analog to digital converters for artificial intelligence

Tiny low power current mode analog to digital converters for artificial intelligence

A method of consolidating genealogy records includes partitioning the records using at least one index file to form one or more partitions, sorting the records in a partition based on a data element in the records, comparing records within a sort range, based on the comparison, identifying same person records, consolidating information in the same person records, receiving a request from a user to view at least a portion of the consolidated information for a particular group of same person records, and sending a file that includes the portion to the user.

Correlating genealogy records systems and methods

A digital decimation filter with programmable frequency notches is disclosed. The digital decimation filter performs integration, differentiation, and scaling to produce a filtered output signal. The differentiation is preformed by a programmable counter. The filter has a control unit that controls the behavior of the filter. The control unit has registers to contain ther values of the frequency notches of the filter. The control unit activates the differentiator based on the value of the frequency notches in order to achieve filtration. The scaling unit uses a register, a bit shifter, and an adder to minimize complexity. The digital decimation filter provides high rejection with low complexity.

Digital decimation filter

An apparatus for sensing the rotation of a brushless DC fan includes the fan and a sense/driver circuit and a capacitance. The sense/driver circuit is coupled to the fan to receive a sense input signal including a fluctuating electrical effect caused by fan commutation events. The sense/driver circuit processes the sense input signal to generate a sense output signal indicative of fan operation. The sense/driver circuit includes an integrated circuit. The integrated circuit includes a sense input pin, a ground return pin, a driver circuit, an integrated filter portion, a filter pin and a level detecting circuit. The capacitance is coupled to the filter pin to provide a filter with the integrated filter portion. The driver circuit includes a control terminal, a first current handling terminal coupled to the sense input pin and a second current handling terminal coupled to provide a ground return pat. The integrated filter portion includes a filter input coupled to at least one of the first and second current handling terminals of the driver circuit, and a filter output for providing a filter output signal to the level detecting circuit. The level detecting circuit generates the sense output signal from the filter output signal. The filter derives the filter output signal indicative of the fan commutation events responsive to receiving a signal at the sense input pin.

Verification of fan operation

An integrated circuit voltage converter containing a capacitive charge pump performing DC to DC conversion is disclosed which detects, either automatically or by an external signal, the onset of a low power consumption situation and switches to a low power consumption mode. In one embodiment, the low power consumption mode is accomplished by reducing the operating frequency of the charge pump. In another embodiment, the switching transistors used to switch the capacitors in the charge pump during a low power consumption mode are smaller than those transistors used to switch the capacitors during its normal operating mode. In another embodiment, the DC to DC converter switches back and forth between a high frequency (burst) mode and a low frequency (low power) mode at intervals. In another embodiment, a combination of the power reduction techniques is used. Various techniques for detecting when a low power consumption mode is appropriate are also described.

Power saving technique for battery powered devices

A successive approximation analog-to-digital converter utilizes an improved high-gain current comparator having a zero input impedance characteristic in combination with an equal current digital-to-analog converter. The zero input impedance comparator permits the use of low power C-MOS switching circuitry by leading the output of the digital-to-analog converter to the zero impedance input of the comparator, thereby overcoming the problem of decreased switching speed associated with high capacitance C-MOS outputs. The zero impedance current comparator includes an improved current-to-voltage converter having an overdrive shunt circuit to reduce quiescent current and to permit higher value load resistors for better gain; and cascaded current cells to provide increased gain.

Successive approximation analog-to-digital converter

Growing community of inventors

Paso Robles, CA, United States of America

Jerry M Collings