Macronix International Co., Ltd.

Jerry Lai

Ming-Chung Liang

Chin-Ta Su

Yu-Lin Yen

Henry Chung

Chia-Chi Chung

A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

Methods of forming planarized multilevel metallization in an integrated circuit

A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features. The first and second polymer layers can be formed using dielectric resolution enhancement coating techniques.

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Hsinchu, Taiwan

Jerry Lai