Honeywell Information Systems Inc.

Jerry L Kindell

Richard T Flynn

Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

Circuit for implementing a digital computer instruction

A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digits from the operand into words containing a maximum of 8 decimal digits for transfer to the execution unit. The execution unit processes the words in accordance with a decimal numeric instruction. The throughput of the system is increased when processing short operands which contain 15 decimal digits or less by apparatus in the decimal unit which detects the short operand and determines the number of cache memory cycles between the cycle the first word of the short operand is received from cache memory and the cycle on which the first assembled word is transferred to the execution unit for processing.

Prediction of number of data words transferred and the cycle at which

In a data processing system, groups of characters to be manipulated in a predetermined manner are transferred between storage units and a central processing unit by apparatus and a method which identifies and corrects a character of a group with sign information superimposed on an identified character position for data entering the central processing unit. After identification of the character position containing the sign information superimposed on a character position, the value of the character in the identified character position is determined by apparatus removing the superimposed sign information and such value is placed in such identified character position in the entering character group. A data string including an identified character position can then be entered in the execution unit of the central processing unit for execution of instructions.

Apparatus for identification and removal of a sign signal character

In a microprogrammed data processing system in which the boundaries of the operands or data strings identified by the descriptors are not constrained to coincide with boundaries of the units of addressable memory space, i.e., words, the time required to retrieve, execute and store operands of a three descriptor instruction, wherein two descriptors define the memory address of the initial operands and the third descriptor defines the memory address of the resulting operand, can be reduced by prefetching the two words which include the boundaries of the operand (data string) identified by the third descriptor. After execution of the instruction, the boundary words of the resulting operand (data string) can have the rewrite data, that is the data of the boundary words which are not part of the resulting operand, and should therefore be retained and inserted in appropriate positions of the appropriate boundary word by a retrieval of the boundary words which do not interrupt the normal data processing sequence.

Apparatus and method for rewrite data insertion in a three descriptor

In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which, in response to a microword indicating that the result of the decimal numeric calculation is a short operand, that is, a predetermined number of words or less, and in accordance with an instruction descriptor, generates a count of the number of words of the resultant operand the decimal unit will transfer to memory.

Short operand alignment and merge operation

In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which is conditioned by the instruction descriptors in advance of receiving the operands to align the decimal digits of the operand words as the words are received by the apparatus from memory. The descriptor information for each operand includes the scale factor, the position of the sign, the position of the most significant character within the word, whether it is a floating point or scaled operand, the number of bits in each decimal character, either 4 or 9 bits, and the length of the operand. The apparatus is conditioned by the descriptor information to align the two operands for processing.

Numeric data fetch - alignment of data including scale factor difference

In a data processing system wherein memory space in a memory unit is divided into addressable locations capable of storing a group of signals of predetermined number called signal words, and wherein an entire word or groups of entire words are exchanged between the memory unit and a central processing unit, more efficient operation of the data processing unit can be obtained if groups of related signals called operands can be stored consecutively in the addressable locations without regard to the word boundaries. Thus, operand boundaries can have arbitrary positions in boundary words. When a word containing an operand boundary is transferred to the central processing unit, non-operand data is also transferred with the word. The non-operand data occurring in the boundary words is removed from the operand signal group and stored in the central processing unit. After manipulation of the operand by the central processing unit, the non-operand data is re-inserted in the boundary words in the signal positions previously occupied and the word group containing the manipulation or resulting operand is stored in the memory location from which it was originally removed.

Apparatus and method in a data processing system for manipulation of

Computer apparatus in a word organized computer system for implementing a single computer instruction for moving a binary number stored in one of a plurality of addressable registers to a designated memory location in a word addressable memory. The binary number is divisible into a maximum of four characters with characters of a given number having either 8 or 9 bits, and a word has 36 bits divisible into four bytes. If the characters have 8 bits, the characters are reformatted so that there is one character per byte. If the characters have 9 bits, they are not reformatted since there is already only one character per byte. The bytes are then shifted so that the byte position containing the most significant character of the binary number occupies a designated byte position in a first word stored in a data out register ready to be read into memory for storage at the designated memory location. After the first word is stored in memory, and if the bytes containing characters of the binary number overflow a word boundary of the first word, bytes containing overflow characters are stored in a second word in the data out register ready for storage at a memory location contiguous to the designated memory location.

Computer apparatus

In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of leading zero digits of an operand on the cycle in which the operand word is processed through the decimal unit and sends that count to the execution unit in response to a predetermined microword. The apparatus counts the number of leading zero digits by first storing in a register the number of words the decimal unit will not send for processing as determined by an instruction descriptor. As the operand is received by the decimal unit, most significant word first, the number of leading zero digits in the operand is added to the register on the same cycle the operand word is processed through the decimal unit, thereby generating a count of the number of zero digits in the operand that the decimal unit will send for processing. This leading zero digit count is available to the firmware in response to a microword command.

Leading zero count formation

In a microprogrammed data processing system the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which indicates to the microprogram the characteristics of the operand being processed. This enables the proper microprogram subroutine; that is, if the operand is a floating point or a scaled number, has 4-bit decimal digits or 9-bit decimal digits, has an overpunched leading sign or trailing sign, has an adjusted length less than or equal to 63 decimal digits, whether the operand is a long or short operand, and whether the resulting operand is equal to zero or has an overflow.

Vector branch indicators to control firmware

In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which receives a long operand, greater than a predetermined number of words, which is the result of the calculation, assembles the resultant operand in accordance with an instruction descriptor, and transfers the resultant operand to memory.

Long operand alignment and merge operation

In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of effective digits in an operand which is the result of a decimal numeric instruction being processed by the system. The apparatus receives operand words the operand's least significant word first, in response to a predetermined microword. The apparatus includes a first register which stores a count of one less than the number of words received; an adder which increments the output of the first register if the word received has a decimal zero in the high order position of the word; and a second register which stores the output of the adder in a word count portion and the number of leading zeros in a digit count portion of the second register. The second register is loaded on the same cycle the word is processed providing the word does not contain all decimal zeros.

Effective digit count on a resultant operand

In a microprogrammed data processing system the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which strips zone bits, sign, exponent and non-operand characters from the operand when the operand is received from memory and appends the zone bits, sign, exponent and non-operand characters to the resultant operand when stored into memory. The control signals for stripping and appending information is enabled by shifter logical elements.

Pointer for defining the data by controlling merge switches

A multiplication apparatus comprises a plurality of multiple generator circuits, each of which simultaneously generates binary signals representative of a predetermined multiple of a multiplicand for different digits of a group of multiplier digits. A different one of the multiple generator circuits couples to a different one of a plurality of serially connected adder circuits for applying the binary signals. Each of the multiple generator circuits includes storage circuits coupled to receive timing signals from a common source to enable an overlap in the generation of binary multiple signals minimizing the number of multiplication cycles required to perform a multiplication operation in response to multiply instructions.

High speed binary multiplication system employing a plurality of

A multiple-generating register generates one of several possible multiples of a binary member which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circuit for generating the multiple-generating commands in response to a three-bit control signal and comprises further a plurality of selector latch logic circuits. Each selector latch logic circuit receives as a first input a respective bit of the input binary number and receives as a second input the next lowest order bit of the input binary number, except that the selector latch logic circuit which receives as a first input the lowest order bit of the input binary number receives as a second input a zero-valued binary bit. The plurality of selector latch logic circuits generate a binary number that is a multiple of the input binary number, which multiple is equal to the input binary number times .+-.1, .+-.2, or 0, depending upon the informational content of the three-bit control signal.

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Glendale, AZ, United States of America

Jerry L Kindell