Texas Instruments Corporation

Burr-brown Corporation

Texas Instruments Tucson Corporation

Jerry Doorenbos

Dimitar Trifonov

Vadim Valerievich Ivanov

Srinivas Kumar Pulijala

Marco A Gardner

YuGuo Wang

Keith Eric Sanborn

David M Jones

Srikanth Vellore Avadhanam Ramamurthy

Mina Raymond Naguib Nashed

Dwight David Griffin

Tathagata Chatterjee

Tony Ray Larson

Munaf Hussain Shaik

Sudarshan Udayashankar

Steven Loveless

David Alexander Gammie

Vivek Varier

Patrick Forster

Tao Peng

Nathan Y Moyal

Baboo V Gowreesunker

Mikhail Valeryevich Ivanov

Bharath Karthik Vasan

David Baum

Abdullah Yilmaz

Ronald F Cormier, Jr

Siva Kumar Sudani

Jeffrey B Parfenchuck

Frank Haupt

Jeffery B Parfenchuck

Sudheer Gangula

Ranga Seshu Paladugu

Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.

Gain and temperature tolerant bandgap voltage reference

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

Class AB monticelli output stage design with bias temperature instability tolerance

In an example, a device includes a semiconductor substrate having a top surface. The device also includes a P-doped well formed in the semiconductor substrate and extending downwardly from the top surface. The device includes a cathode of a diode formed by an N-doped region in the P-doped well. The device also includes an anode of the diode formed by a P-doped region, the P-doped region spaced away from the N-doped region in the P-doped well. The device includes a deep N-type buried layer (DNBL) formed in the semiconductor substrate, the P-doped well formed between the top surface and the DNBL. The device also includes an N-doped well extending from the top surface to the DNBL.

Ultra-low leakage diodes used for low input bias current

An example apparatus includes: An amplifier comprising folded cascode circuitry having an input and an output, an input pair coupled to the input, clamp circuitry including: a first transistor having a first drain, a first source, and a first gate, the first source coupled to the output, a second transistor having a second drain, a second source, and a second gate, the second drain coupled to the first drain and the second gate coupled to the first drain and second drain, a third transistor having a third drain, a third source, and a third gate, the third source coupled to the output, and a fourth transistor having a fourth drain, a fourth source, and a fourth gate, the fourth drain coupled to the third drain and the fourth gate coupled to the third drain and the fourth drain.

Methods and apparatus to improve performance of amplifiers

Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.

Trimming operational amplifiers

Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

Direct current measurement of 1/f transistor noise

In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

Temperature sensing with bandgap sensor input to sigma-delta ADC

Sigma-delta analog-to-digital converter with multiple counters

A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.

First-order sigma-delta analog-to-digital converter

An integrated circuit (IC) chip can include an operational amplifier with adjustable operational parameters. The IC chip can also include a trimming module configured to measure an output voltage of the operational amplifier in response to at least one of detecting that the operational amplifier has a positive supply voltage set to a level greater than a predetermined level and detecting a given common mode voltage at inverting and non-inverting inputs of the operational amplifier. The trimming module can also be configured to adjust the operational parameters of the operational amplifier based on the output voltage to trim the operational amplifier.

Op-amp IC chip

One example includes an reference voltage generator system. The system includes an amplifier configured to generate a reference voltage based on a respective input voltage provided at each of at least one input of the amplifier. The system also includes at least one input transistor that is coupled to the at least one input of the amplifier and is statically-biased to conduct a current to set an amplitude of the respective input voltage provided at each of the at least one input of the amplifier. Each of the at least one input transistor includes an input terminal that is coupled in series with an input resistor.

Reference voltage generator system for reducing noise

Touch screen controllers and methods are presented for removing charger noise and other high frequency noise from touch screens in the presence of aliasing in which a digital low pass filter rejects the high frequency noise, a noise tracker determines whether noise is being aliased into the low pass filter pass band, and a noise shaper artificially induces or modifies aliasing in the system by adjusting an analog-to-digital converter sampling frequency and/or a panel scan frequency to try to move the aliased noise outside the low pass filter pass band.

Touchscreen controller and method for charger noise reduction through noise shaping

An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection electrodes that are spaced apart and electrically isolated from one another and an associated set of interleavers. Each interleaver is located between adjacent detection electrodes from its associated the set of detection electrodes, and each set of interleavers also includes a pair of complementary interleaving electrodes coupled to those that are electrically coupled to the adjacent detection electrodes from its associated set of detection electrodes. The detection electrodes and interleaving electrodes are also substantially transparent to visible spectrum light.

Growing community of inventors

Tucson, AZ, United States of America

Jerry Doorenbos