International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Jerry Don Ackaret

Wilson Earl Smith

James A O'Connor

Sumeet Kochar

Randolph Scot Kolvick

Robert M Dunn

Susan E Goodwin

Gary David Cudak

Michael S Gordon

Michael A Gaynes

Fred Allison Bower, Iii

Justin Potok Bandholz

Scott Barnett Swaney

Martin Joseph Crippen

James Edward Hughes

Nancy C LaBianca

Jeffery Michael Franke

Caihong Zhang

Joseph Edward Bolan

David John Jensen

Jeffery J Van Heuklon

John K Langgood

David F Heidel

Bay Van Nguyen

Derek Robertson

John M Sheplock

Naoko Pia Sanda

Brian E Bigelow

Christopher Lee Durham

Kevin M Cash

Jeffrey J Van Heuklon

Richard B Bhend

Janes Jones, Legal Representative

Barry Eugene Jaked

Jane Jones, Legal Representative

Anna H Siskind

David L Cowell

Managing thermal cycles of air temperature within a server rack includes: monitoring air temperature within the server rack; determining that the monitored temperature has fallen below a predetermined minimum threshold; and increasing air temperature within the server rack including capturing warm ambient air.

Managing air temperature within a server rack

Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Physical memory fault mitigation in a computing environment

Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Managing faulty memory pages in a computing system

Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis ('PFA') module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.

Operating computer memory

A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.

Implementing ultra high availability personality card

An IC device is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined, substantially constant emission rate. The emission rate may be tunable. In one aspect, a radioactive adhesive composition is provided for bonding a semiconductor device to a chip carrier. The radioactive adhesive composition is made from a cured reaction product including a resin and a filler, and may be reworkable or non-reworkable. Either the resin or the filler, individually or both together as a mix, are doped substantially uniformly with the transient-particle-emitting material, thereby putting the transient-particle-emitting in close proximity with the IC to be tested. The underfill is formulated to have a stable chemistry, and the doped particles are encapsulated, so as to contain the emissions. Accelerated transient-particle-emission testing may then be performed on the IC in situ to provide accelerated detection of soft errors.

Packaging integrated circuits for accelerated detection of transient particle induced soft error rates

A system includes a data processing core coupled to a system memory employing error correction code (ECC) circuitry. The core includes an indicator of when a correctable system memory error occurs and what address is associated with the error. A watchdog timer is instantiated on a system management device. Periodically, the timer prompts the management device to interrupt the processor and poll the error indicator to determine if a memory error has been detected. If an error is detected, the corresponding physical memory address is recorded. If a predetermined number of consecutive errors associated with a single memory address or range of addresses occurs, an alert is issued. In one embodiment, polling the error indicator is infrequent initially. As additional errors are detected, the polling frequency increases. At higher polling frequencies, the system may require a greater number of consecutive errors before taking additional action.

Implementing memory failure analysis in a data processing system

A method and system are provided for accelerated detection of soft error rates (SER) in integrated circuits (IC's) due to transient particle emission. An integrated circuit is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined emission rate. The emission rate is substantially constant over a predetermined period of time for testing. Accelerated transient-particle-emission testing is performed on the integrated circuit. Single-event upsets due to soft errors are detected, and a quantitative measurement of SER is determined.

System and method for accelerated detection of transient particle induced soft error rates in integrated circuits

Growing community of inventors

Beaverton, OR, United States of America

Jerry Don Ackaret