Motorola Corporation

Advanced Micro Devices Corporation

Jerry D Moench

Om P Agrawal

Kerry A Ilgenstein

Nicholas A Schmitz

George H Landers

Roger I Kung

Michael K Ciraula

William L Martino, Jr

Rodney C Tesch

Alan J Lewandowski

Scott C Johnson

Bruce L Morton

Mitchell K Alsup

Michael J Wright

Teik-Chung Tan

Arthur H Khu

Ravinder Reddy Rachala

Floyd L Dankert

Victor F Andrade

Alan Richard Bormann

Jan-Michael Huber

Gregory A Constant

James C Pattison

Alexander W Schaefer

Randal L Posey

Michael C Braganza

Frank Arlen Miller

Amy M Novak

Don Walters

Soolin Kao Chrudimsky

Jan Michael Huber

William L Martino

Various embodiments of methods and systems for providing virtual leaf driver nodes in a clock tree to drive a clock grid of an integrated circuit are disclosed. An integrated circuit may include a large number of clocked elements such as registers, flip-flops, etc. whose operation is synchronized by one or more clocks. For example, an operation performed by circuitry on one side of the die may need to occur at precisely the same time as another operation performed by circuitry on the other side of the die. In order to assure synchronicity of these events, a clock grid may be provided in the IC that is driven by virtual leaf driver nodes. The clock tree driving the clock grid may include a tier of leaf buffers. The output of a leaf buffer may be split, and the branches of the output connected to separate points on the clock grid.

Clock grid driven by virtual leaf drivers

A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality of history cells is coupled to receive data from the base cell through a second port.

Multi-ported register cell with randomly accessible history

A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Memory array with global bitline domino read/write scheme

In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plurality of semiconductor devices to have a substantially uniform spacing between each gate structure. The method also includes forming a decoupling capacitor region adjacent to the ACLV controlled region. The decoupling capacitor region may include a plurality of capacitor structures each having a conductive structure, such as a polysilicon electrode, for example.

Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit

A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Each of the plurality of storage blocks may be accessed asynchronously. In addition, the cache subsystem includes a plurality of tag units which are coupled to the plurality of storage blocks. Each of the tag units may be configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within the plurality of storage blocks. Each of the plurality of tag units may be accessed synchronously.

Microprocessor including bank-pipelined cache with asynchronous data blocks

A fuse cell circuit includes a first fuse and a first fuse sense circuit that senses a programming state of the first fuse and supplies an indication thereof. A sense control circuit includes a plurality of reference fuses and a second fuse sense circuit coupled to the reference fuses. The sense control circuit supplies a sense control signal to the fuse cell circuits to cause the fuse cell circuits to sense the programming state of the first fuse when the sense control signal is asserted. The sense control signal is asserted for a time period determined , at least in part, by a resistance value of the reference fuses. The integrated circuit may also include a resistance varying circuit coupled to vary a resistance value of a current path of the reference fuses according to one or more control signals.

Method and apparatus for sensing a programming state of fuses

Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

High density programmable logic device

Family of multiple segmented programmable logic blocks interconnected by

An I/O macrocell for a programmable logic device

The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells. The PLD includes a block clock generation circuit. In the block clock generation circuit, a plurality of programmable block multiplexers provide a plurality of clock signals to a programmable macrocell clock multiplexer in a macrocell of the PLD.

Flexible block clock generation circuit for providing clock signals to

An SRAM array configuration includes even bitline pairs which each laterally interchange at a crossover placed at the 1/2 point along the length of the bitline pairs, and which SRAM array includes odd bitline pairs which each laterally interchange at each of two associated crossovers at the 1/4 and 3/4 points along the length of the bitline pairs. Consequently, signals or noise resident on neighboring bitline pairs or other neighboring conductive structure couple a common-mode voltage onto a given bitline pair through lateral parasitic capacitance to the neighboring conductive structure. Such a common-mode noise signal does not affect the differential signal on the given bitline pair. This interlaced configuration is useful for one or more pairs of differential signal lines, whether used within an SRAM array or for global interconnect between circuit blocks.

Interlaced layout configuration for differential pairs of interconnect

Logic allocator for a programmable logic device

The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells.

Architecture of a multiple array high density programmable logic device

High speed centralized switch matrix for a programmable logic device

The present invention teaches an improved multiplexer system wherein more than one wide bus line may be connected to a single bus line, but wherein only one such wide bus line will be so connected. This system includes structure for imposing ordered consideration of each of the more than one wide bus lines to determine whether it should be connected to the single bus line, structure for enabling connecting of one of the wide bus lines to the single bus line, and structure for disabling possible connection of each of the more than one wide bus lines ordered subsequent to the connected wide bus line.

Switch matrix multiplexers

Growing community of inventors

Austin, TX, United States of America

Jerry D Moench