Advanced Micro Devices Corporation

Other

Jerry Chun-Jen Kuo

Autumn Jane Niu

Po-Shen Lai

Robert Alan Williams

John Mingyung Chiang

Din-I Tsai

Ching Yu

Jeffrey Roy Dwork

Ian Lam

Jenny Liu Fischer

A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

A novel method of power management is provided in a computer system having a network interface module including a buffer memory and a MAC block. The method includes determining whether the system is inactive during a predetermined time period. If so, activity of the MAC block is checked. If the MAC block is idle, the status of the buffer memory is determined. The system is placed into a power-down mode if the buffer memory is empty.

Power management indication mechanism for supporting power saving mode in computer system

A network interface for a workstation is configured to supply data to a host bus. The network interface includes a buffer memory for storing a data frame received from a network according to a first byte alignment. A bus interface unit is configured to output the data frame onto the host bus according to a second byte alignment based on a master or slave transfer request to access the buffer memory. The slave request to access the buffer memory may be in the form of either an I/O mapped or memory mapped request. A memory management unit includes request logic to receive the master and slave transfer requests and generate a generic request to access the buffer memory. The memory management unit is configured to transfer the data frame from the buffer memory in response to the generic request. The bus interface unit includes a byte packing circuit configured for changing a byte alignment of the data frame prior to its transfer to the host memory. The byte alignment is changed based on information associated with the generic request. Hence, the amount of logic necessary to service the various types of requests is minimized.

Network interface for changing byte alignment transferring on a host bus according to master and slave mode memory and I/O mapping requests

A network interface has a static random access memory (SRAM) that outputs ordered data to a target by using a first and second holding register, and an output holding register. The SRAM supplies a data set to the first holding register which supplies the first data set to the second holding register. The SRAM also replenishes the first holding register with a second data set. A multiplexer selectively supplies the data set stored in one of the two holding registers to the output holding register which supplies that data set to a bus connected to the target. A bus interface unit state machine supplies a select signal to the multiplexer to control the selection between the first and second holding registers. The state machine generates the select signal based on a bus access controller detecting a target ready signal generated by the target indicating the target's readiness to receive a data set. The select signal enables the multiplexer to supply the next ordered data set to the output holding register. If the target ready signal is asserted too frequently for the first holding register to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the first holding register to the output holding register. If the target ready signal is asserted relatively infrequently and the first holding register has sufficient time to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the second holding register to the output holding register.

Efficient data loading scheme to minimize PCI bus arbitrations delays and wait states

A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive. The reload address is also supplied to the address register to resume normal addressing by address holding register.

Apparatus and method in a network interface for recovering from complex PCI bus termination conditions

A reception indicator is within a network peripheral that receives information packets for a host system from a communications network. The reception indicator of the present invention allows the network peripheral to operate in one of a plurality of modes. The reception indicator of the present invention asserts an interrupt signal at a respective optimum interrupt time for each of the modes. If the network peripheral is operating in a programmed I/O mode (i.e. a slave mode), a slave optimum interrupt time is determined. In this mode, a host processor unit within the host system reads portions of information packets from a readable data port in a host system interface. In this mode, an interrupt is asserted at the slave optimum interrupt time before a last byte of an information packet is expected to be received from the communications network. If the network peripheral is operating in a DMA (Direct Memory Access) mode, a DMA (Direct Memory Access) optimum interrupt time is determined. In this mode, the network peripheral automatically transfers the received information packet to a host memory of the host system. In this mode, an interrupt signal is asserted at the DMA optimum interrupt time before a last byte of an information packet is expected to be copied to the host memory. In this manner, the present invention allows the network peripheral and the host system to operate in one of the modes that is most efficient for data processing while at the same time issuing an interrupt at a respective optimum interrupt time for each of the modes.

Information packet reception indicator for reducing the utilization of a

A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. A descriptor management unit is used to control DMA reading and writing of transmit data and receive data from and to system memory, respectively, based on descriptor lists, respectively. A pipelining architecture also optimizes transfer of data between the buffers, the PCI bus, and the media access controller.

Network interface device architecture for storing transmit and receive

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

Apparatus and method in a network interface device for storing receiving

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. Use of gray code counters enables asynchronous comparisons to be made between the two counter values, independent of the host computer bus clock domain and the network clock domain.

Apparatus and method for determining a presence of a stored data frame

A network interface device minimizes access latency in initiating a DMA transfer request by selectively supplying a long bit comparison result, generated in a write controller configured for writing data into a buffer memory, directly to a read controller based on a determination that the buffer memory stores less than one complete frame. The media access controller determines the length of the data frame, and supplies the determined length to the write controller. The write controller compares the determined length to a prescribed threshold, and outputs a long bit value for storage in a buffer memory location contiguous with the stored data frame. The long bit can then be used to select a receive buffer threshold optimized for larger frames. If less than one complete frame is stored in the buffer memory, the write controller outputs the long bit information to the read controller, enabling the read controller to initiate a DMA transfer request, using a threshold selected based on the long-bit information, prior to storage of the complete data frame in the buffer memory.

Apparatus and method in a network interface device for selectively

An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine. Thus, the host system returns to the foreground task as soon as possible when the subsequent interrupt is not generated sufficiently close in time from the prior interrupt.

Mechanism for minimizing overhead usage of a host system by polling for

A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing receive frame data received from a media access controller into the random access memory. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller operating in a separate clock domain to access the status information and the corresponding data frame as a single data unit. Moreover, the disclosed embodiment stores the status information at the beginning of the stored data unit, enabling a controller reading the buffer memory to immediately determine the status of the corresponding stored data frame.

Apparatus and method in a network interface device for storing status

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. The determined presence of one or more stored data frames is used to arbitrate storage of tracking information by either the read controller or the write controller into a holding register used to determine a read status for the random access memory.

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San Jose, CA, United States of America

Jerry Chun-Jen Kuo