Xilinx, Inc.

Jerry Chuang

William C Black

Scott Alan Irwin

David Erich Tetzlaff

Scott Allen Davidson

Dai Huang

Jerome M Meyer

A high data rate transceiver for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. The transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

PMA RX in coarse loop for high speed sampling

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module, an aligning module, a selecting module, and a memory module. The oversampling module is operably coupled to oversample an n-bit data word at an oversampling rate of m to produce an m by n bit oversampled data word, wherein the n-bit data word is received at a first data transmission rate that is less than a serial bit rate of the high speed transceiver. The transition boundary module is operably coupled to determine transition boundary data of the m by n bit oversampled data word in accordance with a clock of the high speed transceiver to produce transition boundary data. The selecting module is operably coupled to select representative bits in accordance with the transition boundary data to produce a recovered data word. The memory module is operably coupled to store the recovered data word.

High speed transceiver receiving lower rate data

A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between clock domain boundaries and for maintaining alignment of multiple outputs signals.

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Sunnyvale, CA, United States of America

Jerry Chuang