Advanced Micro Devices Corporation

Jerry Cheng

Fei Wang

Todd P Lukanc

Khoi A Phan

Simon S Chan

Darrell M Erb

Jeffrey P Erhardt

Martin Mazur

Wolfram Grundke

Richard J Bartlett

Daniel E Sutton

Anthony P Coniglio

Carol M Bradway

Lu You

Lynne A Okada

Minh Quoc Tran

Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein, including special vapor prime and development operations.

Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process

For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

Method for forming dual damascene interconnect structure

Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first dielectric layer made of an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first dielectric layer, and a second dielectric layer, made of low k dielectric material, is formed on the nitride etch stop layer. A via is etched into the first dielectric layer, and a trench is then etched into the second dielectric layer. The materials if the first and second dielectric layers are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second dielectric layer and not the first dielectric layer.

Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer

A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer

A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer

A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.

Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer

A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

Self-aligned dual damascene arrangement for metal interconnection with

In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 sccm of CHF.sub.3, about 5 sccm to about 15 sccm of nitrogen and about 80 sccm to about 120 sccm of a carrier gas. In another embodiment, the present invention relates to a method of processing a semiconductor substrate comprising silicon nitride disposed over a copper containing layer, involving etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising CHF.sub.3, nitrogen and Ar.

Nitride etch using N.sub.2 /Ar/CHF.sub.3 chemistry

In one embodiment, the present invention relates to a method of etching tantalum disposed over a dielectric layer, involving etching at least a portion of the tantalum using a tantalum etch gas mixture containing from about 300 sccm to about 400 sccm of CF.sub.4 and about 200 sccm to about 600 sccm of oxygen at a temperature from about 100.degree. C. to about 150.degree. C. under a pressure from about 1 torr to about 1.5 torr. In another embodiment, the present invention relates to a method of etching at least a portion of a tantalum barrier layer, the tantalum barrier layer at least partially surrounding a copper or copper alloy interconnect, involving etching at least a portion of the tantalum barrier layer using a tantalum etch gas mixture containing from about 300 sccm to about 400 sccm of CF.sub.4 and about 200 sccm to about 600 sccm of oxygen.

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Milpitas, CA, United States of America

Jerry Cheng