Taiwan Semiconductor Manufacturing Comp. Ltd.

Jerry Chang-Jui Kao

Chi-Lin Liu

Hui-Zhong Zhuang

Lee-Chung Lu

Shang-Chih Hsieh

Chung-Hsing Wang

Kuo-Nan Yang

Jung-Chan Yang

Yi-Chuin Tsai

Chou-Kun Lin

Chien-Ju Chao

Ting-Wei Chiang

Chi-Yu Lu

Meng-Hung Shen

Li-Chun Tien

Sheng-Hsiung Chen

Chin-Shen Lin

Tzu-Ying Lin

Sung-Yen Yeh

Li-Chung Hsu

Nitesh Katta

Che Min Huang

Stefan Rusu

Fong-yuan Chang

Yung-Chen Chien

Wei-Hsiang Ma

Zhe-Wei Jiang

Cheok-Kei Lei

Po-Chia Lai

Yan-Hao Chen

Yu-Chi Li

Chia-Wei Tseng

Chih-Liang Chen

Po-Hsiang Huang

Yi-Kan Cheng

Ta-Pen Guo

Fong-Yuan Chang

Chun-Chen Chen

Shao-Huan Wang

King-Ho Tam

Yen-Pin Chen

XinYong Wang

Po-Chun Wang

Chi-Yeh Yu

Huan Chi Tseng

Jung-chan Yang

Bor-Tyng Lin

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

Low-power flip flop circuit

An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.

Footprint for multi-bit flip flop

An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Integrated circuit in hybrid row height structure

A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Logic circuits with reduced transistor counts

Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Systems and methods for context aware circuit design

A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Semiconductor device and integrated circuit in hybrid row height structure

In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

Flip-flop with delineated layout for reduced footprint

A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Integrated circuit, system for and method of forming an integrated circuit

A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.

Layout for integrated circuit and the integrated circuit

A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.

A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.

Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Standard cells and variations thereof within a standard cell library

Growing community of inventors

Taipei, Taiwan

Jerry Chang-Jui Kao