Honeywell G.m.b.h.

Jerry C Yue

Michael S Liu

Allan T Hurst, Jr

Gordon Alan Shaw

Tangshiun Yeh

Huang-Joung Chen

A process for forming a magnetoresistive bit and an interconnection to an underlying component forms a pattern in an amorphous dielectric overlying the magnetic materials. Portions of the magnetic materials are removed to form a bit having a smooth bit edge profile by ion milling. The bit has a bit end located over the underlying component. A second amorphous dielectric layer is deposited and etched at the bit end to form a via at the underlying component. Conventional first metal is used to form the interconnection.

Highly producible magnetoresistive RAM process

A frontside gettering method for removing metallic contamination from a thin film SOI or SOS silicon device. Damage sites are created by ion implantation into inactive regions of a silicon substrate. An annealing step causes metallic contamination to diffuse from the active device region to the inactive region. The inactive region material is removed prior to subsequent processing steps.

Method to getter contamination in semiconductor devices

A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.

Fabrication of stabilized polysilicon resistors for SEU control

A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.

Growing community of inventors

Roseville, MN, United States of America

Jerry C Yue