Intel Corporation

Jerry A Kreifels

Rodney R Rozman

Christopher John Haid

Vishram P Dalvi

Jahanshir J Javanifard

Mickey L Fandrich

Virgil N Kynett

Jeffrey J Peterson

Alan E Baker

George Hoekstra

Richard J Durante

Jeff Evertt

Joseph W Tsang

Steven E Wells

Peter K Hazen

Charles W Brown

Mark D Winston

David A Leak

Thomas C Price

Fasil G Bekele

Mamun Ur Rashid

William D Smith

Alexander C Mitchell, Iii

Vishram Prakash Dalvi

A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

Block locking apparatus for flash memory

A flash memory that could not have completed an operation within a time required by a host may be able to work with the host by dividing the operation into phases that may be completed within the allocated time. As a result, a type of memory that would otherwise be unable to be implemented in a format, such as a memory card, may be used effectively.

Dividing a flash memory operation into phases

In some embodiments, an apparatus and methods for storing data which self-compensate for erase performance degradation. Such an apparatus includes, in an exemplary embodiment, a plurality of memory blocks individually erasable during erase cycles by the application of erase pulses thereto having appropriate erase pulse voltage levels, and a memory location uniquely associated with each memory block that stores an initial erase pulse voltage level therefor to be used during an erase cycle. Such methods include, in an exemplary embodiment, counting the number of erase pulses applied to each memory block during an erase cycle therefor, comparing the count for each memory block to a threshold count value, and updating the stored initial erase pulse voltage level to be used during a subsequent erase cycle for each respective memory block if the count for that memory block is not less than the threshold count. Other embodiments are described and claimed.

Apparatus and methods for storing data which self-compensate for erase performance degradation

Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.

Systems with non-volatile memory bit sequence program control

A bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.

Method and apparatus for non-volatile memory bit sequence program controller

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Nonvolatile writeable memory with program suspend command

A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.

Block locking and passcode scheme for flash memory

A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.

Method of programming, erasing, and reading block lock-bits and a master

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Method and apparatus for suspending the writing of a nonvolatile

Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.

Circuitry for propagating test mode signals associated with a memory

A method of enabling access to a test mode of a semiconductor memory in response to user commands. The method enables test mode access only when a number of 'keys' are presented in the proper sequence via the memory device pins. During the first phase of the unlocking process, an array controller determines whether the correct confirmation codes were input via the address and data pins. If they were, the array controller proceeds to the second phase of the unlocking process. During the second phase voltage levels on selected control pins are checked for a transition to a first voltage level. If the control pins transition as required, the array controller proceeds to the third phase. During the third phase, the array controller waits a limited time for receipt of a second test mode enable command. The second test mode enable command must be followed by correct confirmation codes. If the third phase is successfully completed, the array controller writes to a test mode enable access register. As a result, an enable test mode signal becomes active, which allows the user interlace to respond to subsequently issued test mode commands. Also described is a method of eliminating access to the test mode of the semiconductor memory device, which includes a nonvolatile instruction memory.

Method and circuitry for enabling and permanently disabling test mode

A circuit for providing a read only value for an integrated circuit which integrated circuit includes a plurality of layers of material any one of which may be changed if the integrated circuit is revised comprising a pair of conductors positioned closely adjacent one another in each of the layers of material which carries conductors, a first source of voltage connected to one of the conductors on one of the layers for providing a first binary value, a second source of voltage connected to another of the conductors on one of the layers for providing a second binary value, an output terminal on one of the layers, and apparatus for connecting a selected one of the sources to the output terminal through one of the conductors on each of the layers.

Multiple layer programmable layout for version identification

A method of determining erasure characteristics of a nonvolatile semiconductor memory array using an on-board write state machine is described. The method begins by configuring the write state machine to apply a single erase pulse to the array and then issuing an erase command. If array erasure is unsuccessful, another erase command is issued. Erase commands are reissued until every address within the array is successfully erased.

Method for testing erase characteristics of a flash memory array

An apparatus for testing a unit comprising an internal processor coupled to a register by an internal bus. The internal processor is programmed so that it can execute an algorithm. When executed, the algorithm performs an operation on the unit. The register is for storing a state datum. The internal bus is used by the internal processor to access the state datum when the internal processor is executing the algorithm. The testing apparatus comprises an external processor disposed external to the unit and an interface and switch disposed on the unit. The interface is coupled to the internal and external processors and is for receiving a plurality of commands from the external processor. The commands include an internal processor command and an open trap command. If issued, the internal processor command causes the internal processor to execute the algorithm. The switch is coupled to the interface and coupled between the internal processor and the internal bus. If the interface receives the open trap command, the switch permits the external processor to access the state datum of the register.

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El Dorado Hills, CA, United States of America

Jerry A Kreifels