Rockwell International Corporation

Rockwell Semiconductor Systems, Inc.

Rockwell Electronic Commerce Corp.

Jerrold Scott Zdenek

Barry W Jones

Steven T DeLong

A method and apparatus are provided for exchanging control information and voice data between an automatic call distributor and a line card of the automatic call distributor located at a site remote from the automatic call distributor through a wide-bandwidth communication channel. The method includes the step of allocating at least a first portion of the bandwidth of the wide-bandwidth communication channel for the control information and at least a second portion of the bandwidth to voice data. The interprocessor control information is transceived between a controller of the automatic call distributor and a controller of the line card under a packet data format within the first portion of the bandwidth allocated for control information and the voice data is transceived under a dedicated channel format within the second portion of the bandwidth between the automatic call distributor and line card.

Switch voice/data service extension to remote facilities

A time slot interchange having a data channel memory, a channel circuit, having a write address output, the write address output connected to the data channel memory, a signal processing circuit, having a channel input coupled to the data channel memory, a gain input, and an output coupled to the time division multiplexed signal output port, and a connection memory, including a unique read channel field comprising a read address portion and a gain value portion for each data channel to be output by the time slot interchange network. The connection memory has an input connected to the write address output of the channel circuit, a read address output connected to the data channel memory, and a gain value output connected to the gain input of the signal processing circuit.

Timeslot interchange network

A DRAM controller refreshers a DRAM having a maximum refresh interval. The DRAM controller measures a time interval after a refresh cycle, monitors a memory request input of the DRAM for an idle period after a measured time interval of substantially less than the maximum refresh interval, and refreshes the DRAM with a refresh cycle upon detecting one of an idle period and a measured time interval of the maximum refresh interval.

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Riverside, IL, United States of America

Jerrold Scott Zdenek