Silicon Laboratories Inc.

Cirrus Logic Inc.

Crystal Semiconductor Corporation

Lucent Technologies Inc.

Jerrell P Hein

Navdeep S Sooch

Jeffrey William Scott

David R Welland

Axel Thomsen

Yunteng Huang

Marius Goldenberg

Timothy Joseph Dupuis

G Diwakar Vishakhadatta

Andrew W Krone

George Tyson Tuttle

Michael Henderson Perrott

Kenneth J Stern

William G Bliss

G Tyson Tuttle

David E Reed

Russell Croman

Vadim Gutnik

Bruce Philip Del Signore

Srisai Rao Seethamraju

German S Feyh

Rex T Baird

David M Pietruszynski

Qicheng Yu

Akhil K Garlapati

Derrick Chunkai Wei

Ramasubramaniam Ramachandran

Michael Petrowski, Iii

Kenneth Kin Wai Wong

A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Digital hold in a phase-locked loop

A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

Dual loop architecture useful for a programmable clock source and clock multiplier applications

A subscriber line interface circuit apparatus includes tip/ring sense circuitry generating a tip sense signal and a ring sense signal from three sensed currents, wherein the tip sense signal and the ring sense signal correspond to subscriber loop tip and ring currents, respectively. In one embodiment, the tip/ring sense circuitry includes a current mirror generating first and second mirrored sense currents from a first sense current proportional to a battery feed node voltage of a subscriber loop. Current differencing circuitry provides the tip sense signal from a difference between the first mirrored sense current and a second sense current associated with a tip line of the subscriber loop. The current differencing circuitry provides the ring sense signal from a difference between the second mirrored sense current and a third sense current associated with a ring line of the subscriber loop.

Low voltage sensing and control of battery referenced transistors in subscriber loop applications

Methods and apparatus for coupling outgoing analog audio signals to a subscriber line are described. One method includes the step of receiving the outgoing audio signal. The outgoing audio signal is coupled to the subscriber line through a plurality of transistors coupled in a common base configuration. In one embodiment, linefeed driver control signals for controlling battery feed to the subscriber line are received on the same signal lines as the outgoing audio signal. A subscriber line interface circuit apparatus includes a first circuit for coupling a received outgoing audio signal to a subscriber line. The first circuit couples the received outgoing audio signal to the subscriber line through a common base isolation stage. In various embodiments, the common base isolation stage comprises a plurality of bipolar junction transistors coupled in a common base configuration or a plurality of field effect transistors coupled in a common gate configuration.

Subscriber line interface circuitry with common base audio isolation stage

A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating frequency and at frequencies suitable to characterize actual and/or apparent frequency tolerances of the circuit board. The technique maintains transmission line integrity of the on-board clock.

Frequency margin testing

An integrated circuit includes an internal resistance (R) and a compensation circuit coupled to adjust a slice level specified by a slice signal to a compensated slice level according to a difference between the internal resistance (R) and a known resistance (R). A reference voltage is coupled to the internal resistance to generate an internal current and is coupled to the known resistance to generate a known current. The compensated slice level is determined according to the internal current and the known current. The compensated slice level may be generated using an analog to digital converter coupled to a digital to analog converter that scale original slice signal based on the internal and known currents.

Slice voltage compensation

A method includes the step of providing subscriber loop pull-down circuitry operating in a first voltage domain. The subscriber loop pull-down circuitry decreases at least one of a tip and a ring line current in response to a corresponding pull-down control signal. The method further includes the step of providing control circuitry operating in a second voltage domain, wherein the first and second voltage domains are substantially distinct. The control circuitry varies the pull-down control signal to decrease a selected one of the tip and ring line currents in response to a sensed current corresponding to an associated one of a tip pull-down current and a ring pull-down current. A subscriber line interface circuit apparatus includes pull-down circuitry operating in a first voltage domain. The pull-down circuitry varies line currents of the tip and ring lines in response to a pull-down control signal provided by control circuitry operating in a second voltage domain. The first and second voltage domains are substantially distinct. A control isolation stage is coupled to provide the pull-down control signals from the control circuitry to the pull-down circuitry. A feedback isolation stage provides feedback signals from the pull-down circuitry to the control circuitry. The feedback signals represent sensed pull-down currents associated with the tip and ring lines. The control circuitry provides the pull-down control signals for the tip and ring lines in response to the sensed pull-down currents.

A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

Multi-frequency clock synthesizer

A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

Voltage controlled clock synthesizer

A subscriber line interface circuit apparatus includes a signal processor having sense inputs for sensed tip and ring signals of a subscriber loop. The signal processor generates linefeed driver control signals in response to the sensed signals. A linefeed driver provides the sensed tip and ring signals. The linefeed driver drives the subscriber loop in accordance with the linefeed driver control signals.

Subscriber line interface circuitry

In a clock recovery circuit, the output clock from a voltage controlled oscillator is delayed and then provided to a phase detector circuit that generates a difference signal indicating the phase difference between an incoming data stream and the delayed output clock. A loop filter circuit receives the difference signal and supplies a control signal to the oscillator circuit, which varies the output clock according to the control signal. A delay clock circuit receives a delay control signal derived from the difference signal to determine the output clock delay.

Clock and data recovery circuit without jitter peaking

Subscriber line interface circuitry includes an integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop. The integrated circuit generates a subscriber loop linefeed driver control signal in response to the sensed signals. In one embodiment, A linefeed driver includes power circuitry for providing battery feed to the ring and tip nodes of the subscriber loop in accordance with the linefeed control signal. The linefeed driver includes sense circuitry providing a sensed tip signal and a sensed ring signal. The sensed tip and ring signals correspond to a tip current and a ring current of the subscriber loop. In one embodiment, the integrated circuit is a complementary metal oxide semiconductor (CMOS) integrated circuit. In one embodiment, the linefeed driver comprises only discrete components.

A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

Calibration of oscillator devices

Subscriber line interface circuitry includes an integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop. The integrated circuit generates a subscriber loop linefeed driver control signal in response to the sensed signals. The linefeed driver does not reside with the integrated circuit. In one embodiment, the linefeed driver includes power circuitry for providing battery feed to the ring and tip nodes of the subscriber loop in accordance with the linefeed control signal. The linefeed driver includes sense circuitry providing a sensed tip signal and a sensed ring signal. The sensed tip and ring signals correspond to a tip current and a ring current of the subscriber loop. In one embodiment, the integrated circuit is a complementary metal oxide semiconductor (CMOS) integrated circuit. In one embodiment, the linefeed driver comprises only discrete components.

Growing community of inventors

Driftwood, TX, United States of America

Jerrell P Hein