Knuedge, Inc.

Friday Harbor LLC

Jerome Vincent Coffin

Douglas A Palmer

Michael Florea

Andrew White

Douglas B Meyer

William Christensen Clevenger

Ramon Zuniga

Doug Meyer

Michael George Creamer

Silvestre Yrra

An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous 'real' segments or 'chunks' within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.

Disjointed virtual memory scheme with block bypass

A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer. The buffer can be released prior to completion of the data being copied.

Packet router buffer management

A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.

Affinity data collection in a computing system

A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.

DMA engine for transferring data in a network-on-a-chip processor

Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.

Chained packet sequences in a network on a chip architecture

A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed. The thresholds are each set to less than full capacity, so as to indicate that the respective queue is congested, rather than to indicate that they have no space available.

Flow control through packet router

A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. The memory-attached computing resource is configured to read data from the memory and modify the read data prior to either writing the modified data back to the memory, or transmitting the modified data to one or more other of the computing resources, or both.

Memory-attached computing resource in network on a chip architecture to perform calculations on data stored on memory external to the chip

Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Router path selection and creation in a single clock cycle

In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

Synchronization in a multi-processor computing system

A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets.

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San Diego, CA, United States of America

Jerome Vincent Coffin