Agere Systems Guardian Corp.

Lucent Technologies Inc.

Agere Systems Inc.

Jerome Tsu-Rong Chu

Wen Lin

John D LaBarre

Blair Miller

Sidhartha Sen

A metal oxide semiconductor (MOS) capacitor formed according to a process in which Fermi level enhanced oxidation is suppressed by the introduction of nitrogen impurities into an N-doped impurity region is formed to utilize the N-doped impurity region as a lower electrode and includes a capacitor dielectric having a reduced thickness with respect to other portions of the thermal oxide film formed over N-doped impurity regions. The capacitor is highly linear and includes a high capacitance density. The process used to form the capacitor includes thermally oxidizing a substrate such that an oxide film is formed to include multiple thicknesses including an enhanced oxide growth rate producing an oxide film of increased thickness in N-doped impurity regions and a section within nitrogen-doped impurity portions of the N-doped impurity region in which the enhanced oxidation growth is suppressed and the film formed in this region includes a desirably reduced thickness.

Method and structure for modular, highly linear MOS capacitors using nitrogen implantation

The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably includes forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.

Simplified high Q inductor substrate

An inductor for a semiconductor device comprises a plurality of loops connected in series and formed along a lateral axis of the semiconductor device. Each loop comprises a bottom leg, a top leg, and a pair of side legs. The bottom legs are parallel and extend along a first plane. The top legs are also parallel and extend along a second plane. The second plane is parallel to and separate from the first plane. The first and second planes are parallel to said lateral axis, and the side legs are perpendicular to the first and second planes. The top and side legs can be formed from copper. A barrier layer between the top legs and a substrate layer adjacent the top legs and between the side legs and the bottom legs and the substrate layer can also be provided. The barrier can be formed from tantalum.

Lateral high-Q inductor for semiconductor devices

The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably comprises forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.

A method of forming an inductor for a semiconductor device comprises the steps of forming the bottom legs on a first substrate; depositing a second substrate layer over the first substrate; forming the pair of side legs for each loop through the second substrate layer; and, forming top legs connecting pairs of side legs extending from adjacent bottom legs. The step of providing the side legs includes forming a pair of vias through the second substrate layer to the bottom legs, and depositing side legs in the vias. The step of forming the top legs preferably includes forming a channel between the pairs of vias respectively communicating with the adjacent bottom legs, and depositing top legs in the channels. Additionally, the steps of forming the side and top legs are performed concurrently.

Growing community of inventors

Orlando, FL, United States of America

Jerome Tsu-Rong Chu