Xilinx, Inc.

Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Jerome M Meyer

Judy M Gehman

Scott Allen Davidson

David Erich Tetzlaff

Gary Michael Lippert

John M Nystuen

Jerry Chuang

Scott E Greenfield

A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.

Cache system for managing various cache line conditions

The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheral

A method and apparatus for providing clock phase alignment in a transceiver system are disclosed. Circuits are provided for providing clock phase alignment to adjust and align the phase between clock domain boundaries and for maintaining alignment of multiple outputs signals.

Method and apparatus for providing clocking phase alignment in a transceiver system

Methods and structures of performing multi-level comma detection and alignment on an unaligned data stream. Each string of N consecutive bits in the unaligned data stream is monitored for a predetermined byte value. When the predetermined byte value is located, the unaligned data stream is aligned with the predetermined byte value, producing a partially aligned data stream. A string of bytes from the partially aligned data stream is then compared with a predetermined sequence of byte values. When the predetermined sequence is located, the partially aligned data stream is aligned based on the location of the predetermined sequence within the partially aligned data stream. The invention also encompasses multi-level comma detection and alignment circuits that can perform, for example, the previously described inventive methods.

Methods and structures of multi-level comma detection and data alignment in data stream communications

A dedicated protocol generation unit provides the ability to detect validity of data received from a configurable logic block, such as a programmable logic device (PLD). Data valid signaling is provided by the configurable logic block, such that invalid data received from the configurable logic block is replaced with programmable insertion data prior to transmission, while valid data is allowed to be transmitted without replacement. Also, data received by Input/Output (I/O) portions of the dedicated protocol generation unit are compared to programmable data patterns. After a positive comparison, matching data is either truncated and not delivered to the configurable logic block, or the matching data is delivered to the configurable logic block with appropriate data valid signaling.

Growing community of inventors

Chanhassen, MN, United States of America

Jerome M Meyer